derek.holloway
7502bf64a4
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218 lines
5.7 KiB
YAML
218 lines
5.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test that we can produce a TBNZ when we have a slt compare against 0.
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#
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# The bit tested should be the size of the test register minus 1.
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#
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...
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---
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name: tbnzx_slt
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: tbnzx_slt
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr64 = COPY $x0
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; CHECK-NEXT: TBNZX %copy, 63, %bb.1
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s64) = COPY $x0
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%zero:gpr(s64) = G_CONSTANT i64 0
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%cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s64), %zero
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G_BRCOND %cmp, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: tbnzw_slt
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: tbnzw_slt
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: TBNZW %copy, 31, %bb.1
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s32) = COPY $w0
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%zero:gpr(s32) = G_CONSTANT i32 0
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%cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %zero
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G_BRCOND %cmp, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: tbnzx_sge
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: tbnzx_sge
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr64 = COPY $x0
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; CHECK-NEXT: TBZX %copy, 63, %bb.1
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s64) = COPY $x0
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%zero:gpr(s64) = G_CONSTANT i64 0
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%cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s64), %zero
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G_BRCOND %cmp, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: tbnzw_sge
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: tbnzw_sge
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32 = COPY $w0
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; CHECK-NEXT: TBZW %copy, 31, %bb.1
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s32) = COPY $w0
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%zero:gpr(s32) = G_CONSTANT i32 0
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%cmp:gpr(s32) = G_ICMP intpred(sge), %copy(s32), %zero
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G_BRCOND %cmp, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: no_tbnz_not_zero
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: no_tbnz_not_zero
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr32sp = COPY $w0
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; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %copy, 1, 0, implicit-def $nzcv
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; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s32) = COPY $w0
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%one:gpr(s32) = G_CONSTANT i32 1
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%cmp:gpr(s32) = G_ICMP intpred(slt), %copy(s32), %one
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G_BRCOND %cmp, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: dont_fold_and
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: dont_fold_and
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr64 = COPY $x0
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; CHECK-NEXT: [[ANDSXri:%[0-9]+]]:gpr64 = ANDSXri %copy, 8000, implicit-def $nzcv
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; CHECK-NEXT: Bcc 4, %bb.1, implicit $nzcv
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s64) = COPY $x0
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%bit:gpr(s64) = G_CONSTANT i64 8
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%zero:gpr(s64) = G_CONSTANT i64 0
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%c:gpr(s64) = G_CONSTANT i64 8
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%and:gpr(s64) = G_AND %copy, %bit
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%cmp:gpr(s32) = G_ICMP intpred(slt), %and(s64), %zero
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G_BRCOND %cmp, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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...
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---
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name: dont_commute
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alignment: 4
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legalized: true
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regBankSelected: true
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body: |
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; CHECK-LABEL: name: dont_commute
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.0(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:gpr64 = COPY $x0
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; CHECK-NEXT: %zero:gpr64 = COPY $xzr
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; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %zero, %copy, implicit-def $nzcv
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; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
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; CHECK-NEXT: B %bb.0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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successors: %bb.0, %bb.1
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liveins: $x0
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%copy:gpr(s64) = COPY $x0
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%zero:gpr(s64) = G_CONSTANT i64 0
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%cmp:gpr(s32) = G_ICMP intpred(slt), %zero, %copy(s64)
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G_BRCOND %cmp, %bb.1
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G_BR %bb.0
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bb.1:
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RET_ReallyLR
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