derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
343 lines
9.9 KiB
YAML
343 lines
9.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
|
|
#
|
|
# Test that we can select G_TRN1 and G_TRN2.
|
|
#
|
|
# Each testcase is named based off of the instruction which should be selected.
|
|
|
|
...
|
|
---
|
|
name: TRN1v2i32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1
|
|
; CHECK-LABEL: name: TRN1v2i32
|
|
; CHECK: liveins: $d0, $d1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
|
; CHECK-NEXT: [[TRN1v2i32_:%[0-9]+]]:fpr64 = TRN1v2i32 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $d0 = COPY [[TRN1v2i32_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:fpr(<2 x s32>) = COPY $d0
|
|
%1:fpr(<2 x s32>) = COPY $d1
|
|
%2:fpr(<2 x s32>) = G_TRN1 %0, %1
|
|
$d0 = COPY %2(<2 x s32>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: TRN1v2i64
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $q1
|
|
; CHECK-LABEL: name: TRN1v2i64
|
|
; CHECK: liveins: $q0, $q1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
|
; CHECK-NEXT: [[TRN1v2i64_:%[0-9]+]]:fpr128 = TRN1v2i64 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $q0 = COPY [[TRN1v2i64_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<2 x s64>) = COPY $q0
|
|
%1:fpr(<2 x s64>) = COPY $q1
|
|
%2:fpr(<2 x s64>) = G_TRN1 %0, %1
|
|
$q0 = COPY %2(<2 x s64>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: TRN1v4i16
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1
|
|
; CHECK-LABEL: name: TRN1v4i16
|
|
; CHECK: liveins: $d0, $d1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
|
; CHECK-NEXT: [[TRN1v4i16_:%[0-9]+]]:fpr64 = TRN1v4i16 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $d0 = COPY [[TRN1v4i16_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:fpr(<4 x s16>) = COPY $d0
|
|
%1:fpr(<4 x s16>) = COPY $d1
|
|
%2:fpr(<4 x s16>) = G_TRN1 %0, %1
|
|
$d0 = COPY %2(<4 x s16>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: TRN1v4i32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $q1
|
|
; CHECK-LABEL: name: TRN1v4i32
|
|
; CHECK: liveins: $q0, $q1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
|
; CHECK-NEXT: [[TRN1v4i32_:%[0-9]+]]:fpr128 = TRN1v4i32 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $q0 = COPY [[TRN1v4i32_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<4 x s32>) = COPY $q0
|
|
%1:fpr(<4 x s32>) = COPY $q1
|
|
%2:fpr(<4 x s32>) = G_TRN1 %0, %1
|
|
$q0 = COPY %2(<4 x s32>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: TRN1v8i8
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1
|
|
; CHECK-LABEL: name: TRN1v8i8
|
|
; CHECK: liveins: $d0, $d1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
|
; CHECK-NEXT: [[TRN1v8i8_:%[0-9]+]]:fpr64 = TRN1v8i8 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $d0 = COPY [[TRN1v8i8_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:fpr(<8 x s8>) = COPY $d0
|
|
%1:fpr(<8 x s8>) = COPY $d1
|
|
%2:fpr(<8 x s8>) = G_TRN1 %0, %1
|
|
$d0 = COPY %2(<8 x s8>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: TRN1v8i16
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $q1
|
|
; CHECK-LABEL: name: TRN1v8i16
|
|
; CHECK: liveins: $q0, $q1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
|
; CHECK-NEXT: [[TRN1v8i16_:%[0-9]+]]:fpr128 = TRN1v8i16 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $q0 = COPY [[TRN1v8i16_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<8 x s16>) = COPY $q0
|
|
%1:fpr(<8 x s16>) = COPY $q1
|
|
%2:fpr(<8 x s16>) = G_TRN1 %0, %1
|
|
$q0 = COPY %2(<8 x s16>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: TRN1v16i8
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $q1
|
|
; CHECK-LABEL: name: TRN1v16i8
|
|
; CHECK: liveins: $q0, $q1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
|
; CHECK-NEXT: [[TRN1v16i8_:%[0-9]+]]:fpr128 = TRN1v16i8 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $q0 = COPY [[TRN1v16i8_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<16 x s8>) = COPY $q0
|
|
%1:fpr(<16 x s8>) = COPY $q1
|
|
%2:fpr(<16 x s8>) = G_TRN1 %0, %1
|
|
$q0 = COPY %2(<16 x s8>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: TRN2v2i32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1
|
|
; CHECK-LABEL: name: TRN2v2i32
|
|
; CHECK: liveins: $d0, $d1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
|
; CHECK-NEXT: [[TRN2v2i32_:%[0-9]+]]:fpr64 = TRN2v2i32 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $d0 = COPY [[TRN2v2i32_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:fpr(<2 x s32>) = COPY $d0
|
|
%1:fpr(<2 x s32>) = COPY $d1
|
|
%2:fpr(<2 x s32>) = G_TRN2 %0, %1
|
|
$d0 = COPY %2(<2 x s32>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: TRN2v2i64
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $q1
|
|
; CHECK-LABEL: name: TRN2v2i64
|
|
; CHECK: liveins: $q0, $q1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
|
; CHECK-NEXT: [[TRN2v2i64_:%[0-9]+]]:fpr128 = TRN2v2i64 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $q0 = COPY [[TRN2v2i64_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<2 x s64>) = COPY $q0
|
|
%1:fpr(<2 x s64>) = COPY $q1
|
|
%2:fpr(<2 x s64>) = G_TRN2 %0, %1
|
|
$q0 = COPY %2(<2 x s64>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: TRN2v4i16
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1
|
|
; CHECK-LABEL: name: TRN2v4i16
|
|
; CHECK: liveins: $d0, $d1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
|
; CHECK-NEXT: [[TRN2v4i16_:%[0-9]+]]:fpr64 = TRN2v4i16 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $d0 = COPY [[TRN2v4i16_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:fpr(<4 x s16>) = COPY $d0
|
|
%1:fpr(<4 x s16>) = COPY $d1
|
|
%2:fpr(<4 x s16>) = G_TRN2 %0, %1
|
|
$d0 = COPY %2(<4 x s16>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: TRN2v4i32
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $q1
|
|
; CHECK-LABEL: name: TRN2v4i32
|
|
; CHECK: liveins: $q0, $q1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
|
; CHECK-NEXT: [[TRN2v4i32_:%[0-9]+]]:fpr128 = TRN2v4i32 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $q0 = COPY [[TRN2v4i32_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<4 x s32>) = COPY $q0
|
|
%1:fpr(<4 x s32>) = COPY $q1
|
|
%2:fpr(<4 x s32>) = G_TRN2 %0, %1
|
|
$q0 = COPY %2(<4 x s32>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: TRN2v8i8
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $d0, $d1
|
|
; CHECK-LABEL: name: TRN2v8i8
|
|
; CHECK: liveins: $d0, $d1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
|
|
; CHECK-NEXT: [[TRN2v8i8_:%[0-9]+]]:fpr64 = TRN2v8i8 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $d0 = COPY [[TRN2v8i8_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $d0
|
|
%0:fpr(<8 x s8>) = COPY $d0
|
|
%1:fpr(<8 x s8>) = COPY $d1
|
|
%2:fpr(<8 x s8>) = G_TRN2 %0, %1
|
|
$d0 = COPY %2(<8 x s8>)
|
|
RET_ReallyLR implicit $d0
|
|
|
|
...
|
|
---
|
|
name: TRN2v8i16
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $q1
|
|
; CHECK-LABEL: name: TRN2v8i16
|
|
; CHECK: liveins: $q0, $q1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
|
; CHECK-NEXT: [[TRN2v8i16_:%[0-9]+]]:fpr128 = TRN2v8i16 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $q0 = COPY [[TRN2v8i16_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<8 x s16>) = COPY $q0
|
|
%1:fpr(<8 x s16>) = COPY $q1
|
|
%2:fpr(<8 x s16>) = G_TRN2 %0, %1
|
|
$q0 = COPY %2(<8 x s16>)
|
|
RET_ReallyLR implicit $q0
|
|
|
|
...
|
|
---
|
|
name: TRN2v16i8
|
|
alignment: 4
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $q0, $q1
|
|
; CHECK-LABEL: name: TRN2v16i8
|
|
; CHECK: liveins: $q0, $q1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
|
|
; CHECK-NEXT: [[TRN2v16i8_:%[0-9]+]]:fpr128 = TRN2v16i8 [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: $q0 = COPY [[TRN2v16i8_]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $q0
|
|
%0:fpr(<16 x s8>) = COPY $q0
|
|
%1:fpr(<16 x s8>) = COPY $q1
|
|
%2:fpr(<16 x s8>) = G_TRN2 %0, %1
|
|
$q0 = COPY %2(<16 x s8>)
|
|
RET_ReallyLR implicit $q0
|