derek.holloway
7502bf64a4
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56 lines
1.6 KiB
YAML
56 lines
1.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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#
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# Check that we can select G_UZP1 and G_UZP2 via the tablegen importer.
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#
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# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: uzp1_v4s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0, $q1
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; CHECK-LABEL: name: uzp1_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK-NEXT: [[UZP1v4i32_:%[0-9]+]]:fpr128 = UZP1v4i32 [[COPY]], [[COPY1]]
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; CHECK-NEXT: $q0 = COPY [[UZP1v4i32_]]
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%2:fpr(<4 x s32>) = G_UZP1 %0, %1
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: uzp2_v4s32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $q0, $q1
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; CHECK-LABEL: name: uzp2_v4s32
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK-NEXT: [[UZP2v4i32_:%[0-9]+]]:fpr128 = UZP2v4i32 [[COPY]], [[COPY1]]
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; CHECK-NEXT: $q0 = COPY [[UZP2v4i32_]]
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%0:fpr(<4 x s32>) = COPY $q0
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%1:fpr(<4 x s32>) = COPY $q1
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%2:fpr(<4 x s32>) = G_UZP2 %0, %1
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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