derek.holloway
7502bf64a4
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326 lines
9.2 KiB
YAML
326 lines
9.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: zextload_s32_from_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s16
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
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; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(i32) = G_ZEXTLOAD %0 :: (load (s16))
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$w0 = COPY %1(i32)
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...
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---
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name: zextload_s32_from_s16_not_combined
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s16_not_combined
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
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; CHECK-NEXT: $w0 = COPY [[COPY1]]
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%0:gpr(p0) = COPY $x0
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%1:gpr(s16) = G_LOAD %0 :: (load (s16))
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%2:gpr(i32) = G_ZEXT %1
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$w0 = COPY %2(i32)
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...
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---
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name: i32_to_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: i32_to_i64
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[COPY]], 0 :: (load (s32))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRWui]], %subreg.sub_32
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; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (s32))
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$x0 = COPY %2(i64)
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RET_ReallyLR implicit $x0
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...
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---
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name: i16_to_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: i16_to_i64
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRHHui]], %subreg.sub_32
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; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (s16))
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$x0 = COPY %2(i64)
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RET_ReallyLR implicit $x0
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...
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---
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name: i8_to_i64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: i8_to_i64
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
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; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG [[LDRBBui]], %subreg.sub_32
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; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i64) = G_ZEXTLOAD %0(p0) :: (load (s8))
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$x0 = COPY %2(i64)
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RET_ReallyLR implicit $x0
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...
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---
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name: i8_to_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: i8_to_i32
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
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; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load (s8))
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$w0 = COPY %2(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: i16_to_i32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: i16_to_i32
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load (s16))
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; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load (s16))
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$w0 = COPY %2(i32)
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RET_ReallyLR implicit $w0
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...
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---
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name: zextload_s32_from_s8_atomic_unordered
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s8_atomic_unordered
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load unordered (s8))
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; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load unordered (s8))
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$w0 = COPY %2
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RET_ReallyLR implicit $w0
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...
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---
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name: zextload_s32_from_s8_atomic_monotonic
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s8_atomic_monotonic
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load monotonic (s8))
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; CHECK-NEXT: $w0 = COPY [[LDRBBui]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s8))
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$w0 = COPY %2
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RET_ReallyLR implicit $w0
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...
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---
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name: zextload_s32_from_s8_atomic_acquire
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s8_atomic_acquire
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load acquire (s8))
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; CHECK-NEXT: $w0 = COPY [[LDARB]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load acquire (s8))
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$w0 = COPY %2
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RET_ReallyLR implicit $w0
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...
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---
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name: zextload_s32_from_s8_atomic_seq_cst
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s8_atomic_seq_cst
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDARB:%[0-9]+]]:gpr32 = LDARB [[COPY]] :: (load seq_cst (s8))
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; CHECK-NEXT: $w0 = COPY [[LDARB]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s8))
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$w0 = COPY %2
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RET_ReallyLR implicit $w0
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...
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---
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name: zextload_s32_from_s16_atomic_unordered
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s16_atomic_unordered
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load unordered (s16))
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; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load unordered (s16))
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$w0 = COPY %2
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RET_ReallyLR implicit $w0
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...
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---
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name: zextload_s32_from_s16_atomic_monotonic
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s16_atomic_monotonic
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load monotonic (s16))
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; CHECK-NEXT: $w0 = COPY [[LDRHHui]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load monotonic (s16))
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$w0 = COPY %2
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RET_ReallyLR implicit $w0
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...
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---
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name: zextload_s32_from_s16_atomic_acquire
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s16_atomic_acquire
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load acquire (s16))
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; CHECK-NEXT: $w0 = COPY [[LDARH]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load acquire (s16))
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$w0 = COPY %2
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RET_ReallyLR implicit $w0
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...
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---
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name: zextload_s32_from_s16_atomic_seq_cst
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: zextload_s32_from_s16_atomic_seq_cst
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; CHECK: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[LDARH:%[0-9]+]]:gpr32 = LDARH [[COPY]] :: (load seq_cst (s16))
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; CHECK-NEXT: $w0 = COPY [[LDARH]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:gpr(p0) = COPY $x0
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%2:gpr(i32) = G_ZEXTLOAD %0(p0) :: (load seq_cst (s16))
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$w0 = COPY %2
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RET_ReallyLR implicit $w0
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...
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