derek.holloway
7502bf64a4
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99 lines
3.5 KiB
LLVM
99 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple aarch64 -O0 -stop-after=instruction-select -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
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%dag = type { { { i8, { i8 } }, { { i8, { i8 } }, { i8 } } }, { { i8, { i8 } }, { i8 } } }
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define void @test_const(ptr %dst) {
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; CHECK-LABEL: name: test_const
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; CHECK: bb.1.entry:
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 10
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; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (i8) into %ir.dst)
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; CHECK-NEXT: [[MOVi32imm1:%[0-9]+]]:gpr32 = MOVi32imm 20
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; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (i8) into %ir.dst + 1)
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; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (i8) into %ir.dst + 2)
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; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (i8) into %ir.dst + 3)
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; CHECK-NEXT: [[MOVi32imm2:%[0-9]+]]:gpr32 = MOVi32imm 50
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; CHECK-NEXT: STRBBui [[MOVi32imm2]], [[COPY]], 4 :: (store (i8) into %ir.dst + 4)
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; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (i8) into %ir.dst + 5)
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; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (i8) into %ir.dst + 6)
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; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (i8) into %ir.dst + 7)
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; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 0 :: (store (i8) into %ir.dst)
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; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 1 :: (store (i8) into %ir.dst + 1)
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; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 2 :: (store (i8) into %ir.dst + 2)
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; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 3 :: (store (i8) into %ir.dst + 3)
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; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 4 :: (store (i8) into %ir.dst + 4)
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; CHECK-NEXT: STRBBui [[MOVi32imm]], [[COPY]], 5 :: (store (i8) into %ir.dst + 5)
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; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 6 :: (store (i8) into %ir.dst + 6)
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; CHECK-NEXT: STRBBui [[MOVi32imm1]], [[COPY]], 7 :: (store (i8) into %ir.dst + 7)
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; CHECK-NEXT: RET_ReallyLR
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entry:
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%updated = insertvalue
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; Check that we're visiting constants with shared parts
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; (deduplicated via LLVMContext, forming a proper DAG) correctly:
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%dag {
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{ { i8, { i8 } }, { { i8, { i8 } }, { i8 } } } {
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{ i8, { i8 } } {
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i8 10,
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{ i8 } { i8 20 }
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},
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{ { i8, { i8 } }, { i8 } } {
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{ i8, { i8 } } {
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i8 10,
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{ i8 } { i8 20 }
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},
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{ i8 } { i8 20 }
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}
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},
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{ { i8, { i8 } }, { i8 } } {
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{ i8, { i8 } } {
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i8 10,
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{ i8 } { i8 20 }
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},
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{ i8 } { i8 20 }
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}
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},
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{ { i8, { i8 } }, { i8 } } {
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{ i8, { i8 } } {
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i8 10,
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{ i8 } { i8 20 }
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},
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{ i8 } { i8 50 }
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},
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0,
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1
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store %dag %updated, ptr %dst
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; 10, 20, 10, 20, 50, 10, 20, 20 sequence is expected
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store
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; Check that we didn't overwrite a previously seen constant
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; while processing an insertvalue into it:
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%dag {
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{ { i8, { i8 } }, { { i8, { i8 } }, { i8 } } } {
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{ i8, { i8 } } {
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i8 10,
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{ i8 } { i8 20 }
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},
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{ { i8, { i8 } }, { i8 } } {
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{ i8, { i8 } } {
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i8 10,
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{ i8 } { i8 20 }
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},
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{ i8 } { i8 20 }
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}
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},
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{ { i8, { i8 } }, { i8 } } {
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{ i8, { i8 } } {
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i8 10,
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{ i8 } { i8 20 }
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},
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{ i8 } { i8 20 }
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}
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},
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ptr %dst
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; 10, 20, 10, 20, 20, 10, 20, 20 sequence is expected
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ret void
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}
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