derek.holloway
7502bf64a4
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75 lines
3.2 KiB
LLVM
75 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=arm64-apple-ios %s -o - -global-isel -global-isel-abort=1 -stop-after=irtranslator | FileCheck %s
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define i128 @func_i128(ptr %ptr) {
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; CHECK-LABEL: name: func_i128
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(i128) = G_LOAD [[COPY]](p0) :: (load (i128) from %ir.ptr)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[LOAD]](i128)
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; CHECK-NEXT: $x0 = COPY [[UV]](i64)
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; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
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%val = load i128, ptr %ptr
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ret i128 %val
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}
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define <8 x float> @func_v8f32(ptr %ptr) {
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; CHECK-LABEL: name: func_v8f32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x f32>) = G_LOAD [[COPY]](p0) :: (load (<8 x f32>) from %ir.ptr)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x f32>), [[UV1:%[0-9]+]]:_(<4 x f32>) = G_UNMERGE_VALUES [[LOAD]](<8 x f32>)
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; CHECK-NEXT: $q0 = COPY [[UV]](<4 x f32>)
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; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x f32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
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%val = load <8 x float>, ptr %ptr
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ret <8 x float> %val
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}
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; A bit weird, but s0-s5 is what SDAG does too.
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define <6 x float> @func_v6f32(ptr %ptr) {
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; CHECK-LABEL: name: func_v6f32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<6 x f32>) = G_LOAD [[COPY]](p0) :: (load (<6 x f32>) from %ir.ptr, align 32)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32), [[UV4:%[0-9]+]]:_(f32), [[UV5:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[LOAD]](<6 x f32>)
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; CHECK-NEXT: $s0 = COPY [[UV]](f32)
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; CHECK-NEXT: $s1 = COPY [[UV1]](f32)
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; CHECK-NEXT: $s2 = COPY [[UV2]](f32)
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; CHECK-NEXT: $s3 = COPY [[UV3]](f32)
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; CHECK-NEXT: $s4 = COPY [[UV4]](f32)
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; CHECK-NEXT: $s5 = COPY [[UV5]](f32)
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; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1, implicit $s2, implicit $s3, implicit $s4, implicit $s5
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%val = load <6 x float>, ptr %ptr
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ret <6 x float> %val
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}
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define i128 @ABIi128(i128 %arg1) {
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; CHECK-LABEL: name: ABIi128
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; CHECK: bb.1 (%ir-block.0):
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; CHECK-NEXT: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(i64) = COPY $x0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(i64) = COPY $x1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(i128) = G_MERGE_VALUES [[COPY]](i64), [[COPY1]](i64)
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; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(f128) = G_BITCAST [[MV]](i128)
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; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:_(i128) = G_FPTOUI [[BITCAST]](f128)
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(i64), [[UV1:%[0-9]+]]:_(i64) = G_UNMERGE_VALUES [[FPTOUI]](i128)
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; CHECK-NEXT: $x0 = COPY [[UV]](i64)
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; CHECK-NEXT: $x1 = COPY [[UV1]](i64)
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; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
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%farg1 = bitcast i128 %arg1 to fp128
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%res = fptoui fp128 %farg1 to i128
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ret i128 %res
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}
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