TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/aarch64-condopt-cross-block-different-regs.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=aarch64-condopt -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -mtriple=aarch64-linux-gnu -passes=aarch64-condopt %s -o - | FileCheck %s

# Test that the cross-block condition optimisation in aarch64-condopt does not
# modify compares that use different registers.
#
# This MIR test uses virtual registers that trace back to different physical
# registers via COPY, exercising the lookThruCopyLike() logic.

---
# Negative test: cross-block compares with different source registers should
# NOT be optimised. %0 traces to $w0, %1 traces to $w1.
name:            cross_block_different_regs
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr32sp }
  - { id: 1, class: gpr32sp }
body:             |
  ; CHECK-LABEL: name: cross_block_different_regs
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $w0, $w1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32sp = COPY $w1
  ; CHECK-NEXT:   dead $wzr = SUBSWri [[COPY]], 11, 0, implicit-def $nzcv
  ; CHECK-NEXT:   Bcc 11, %bb.1, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   dead $wzr = SUBSWri [[COPY1]], 10, 0, implicit-def $nzcv
  ; CHECK-NEXT:   Bcc 11, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   $w0 = MOVi32imm 0
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   $w0 = MOVi32imm 1
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    liveins: $w0, $w1
    successors: %bb.1, %bb.2

    %0:gpr32sp = COPY $w0
    %1:gpr32sp = COPY $w1
    dead $wzr = SUBSWri %0, 11, 0, implicit-def $nzcv
    Bcc 11, %bb.1, implicit $nzcv
    B %bb.2

  bb.1:
    successors: %bb.2, %bb.3

    dead $wzr = SUBSWri %1, 10, 0, implicit-def $nzcv
    Bcc 11, %bb.3, implicit $nzcv
    B %bb.2

  bb.2:
    $w0 = MOVi32imm 0
    RET_ReallyLR implicit $w0

  bb.3:
    $w0 = MOVi32imm 1
    RET_ReallyLR implicit $w0
...

---
# Positive test: cross-block compares with the SAME source register SHOULD be
# optimised. Both %0 and %1 trace back to $w0.
name:            cross_block_same_reg
tracksRegLiveness: true
registers:
  - { id: 0, class: gpr32sp }
  - { id: 1, class: gpr32sp }
body:             |
  ; CHECK-LABEL: name: cross_block_same_reg
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT:   liveins: $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32sp = COPY $w0
  ; CHECK-NEXT:   dead $wzr = SUBSWri [[COPY]], 10, 0, implicit-def $nzcv
  ; CHECK-NEXT:   Bcc 13, %bb.1, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   dead $wzr = SUBSWri [[COPY1]], 10, 0, implicit-def $nzcv
  ; CHECK-NEXT:   Bcc 11, %bb.3, implicit $nzcv
  ; CHECK-NEXT:   B %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   $w0 = MOVi32imm 0
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   $w0 = MOVi32imm 1
  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
  bb.0:
    liveins: $w0
    successors: %bb.1, %bb.2

    %0:gpr32sp = COPY $w0
    %1:gpr32sp = COPY $w0
    dead $wzr = SUBSWri %0, 11, 0, implicit-def $nzcv
    Bcc 11, %bb.1, implicit $nzcv
    B %bb.2

  bb.1:
    successors: %bb.2, %bb.3

    dead $wzr = SUBSWri %1, 10, 0, implicit-def $nzcv
    Bcc 11, %bb.3, implicit $nzcv
    B %bb.2

  bb.2:
    $w0 = MOVi32imm 0
    RET_ReallyLR implicit $w0

  bb.3:
    $w0 = MOVi32imm 1
    RET_ReallyLR implicit $w0
...