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65 lines
2.2 KiB
YAML
65 lines
2.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=aarch64-linux-gnu -run-pass=aarch64-condopt -verify-machineinstrs %s -o - | FileCheck %s
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# RUN: llc -mtriple=aarch64-linux-gnu -passes=aarch64-condopt %s -o - | FileCheck %s
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---
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# Negative test: cross-block compares with different physical registers should
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# NOT be optimised. bb.0 compares $w0, bb.1 compares $w1.
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name: cross_block_different_regs
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: cross_block_different_regs
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $w0, $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32common = COPY $w0
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; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 11, 0, implicit-def $nzcv
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; CHECK-NEXT: [[FJCVTZS:%[0-9]+]]:gpr32 = FJCVTZS [[COPY]], implicit-def $nzcv, implicit $fpcr
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; CHECK-NEXT: Bcc 11, %bb.1, implicit $nzcv
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 10, 0, implicit-def $nzcv
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; CHECK-NEXT: Bcc 11, %bb.3, implicit $nzcv
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: $w0 = MOVi32imm 0
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: $w0 = MOVi32imm 1
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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bb.0:
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liveins: $w0, $d0
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successors: %bb.1, %bb.2
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%2:fpr64 = COPY $d0
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%0:gpr32common = COPY $w0
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%1:gpr32 = SUBSWri %0, 11, 0, implicit-def $nzcv
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%4:gpr32 = FJCVTZS %2, implicit-def $nzcv, implicit $fpcr
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Bcc 11, %bb.1, implicit $nzcv
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B %bb.2
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bb.1:
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liveins: $d0
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successors: %bb.2, %bb.3
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%3:gpr32 = SUBSWri %0, 10, 0, implicit-def $nzcv
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Bcc 11, %bb.3, implicit $nzcv
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B %bb.2
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bb.2:
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$w0 = MOVi32imm 0
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RET_ReallyLR implicit $w0
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bb.3:
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$w0 = MOVi32imm 1
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RET_ReallyLR implicit $w0
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...
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