derek.holloway
7502bf64a4
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460 lines
12 KiB
LLVM
460 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
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;
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; trunc(abs(sub(zext(a),zext(b)))) -> abdu(a,b)
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;
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define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: abd_ext_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: subs w8, w8, w1, uxtb
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%aext = zext i8 %a to i64
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%bext = zext i8 %b to i64
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%sub = sub i64 %aext, %bext
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%abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
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%trunc = trunc i64 %abs to i8
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ret i8 %trunc
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}
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define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
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; CHECK-LABEL: abd_ext_i8_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: subs w8, w8, w1, uxth
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%aext = zext i8 %a to i64
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%bext = zext i16 %b to i64
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%sub = sub i64 %aext, %bext
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%abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
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%trunc = trunc i64 %abs to i8
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ret i8 %trunc
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}
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define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: abd_ext_i8_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: subs w8, w8, w1, uxtb
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%aext = zext i8 %a to i64
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%bext = zext i8 %b to i64
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%sub = sub i64 %aext, %bext
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%abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
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%trunc = trunc i64 %abs to i8
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ret i8 %trunc
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}
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define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
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; CHECK-LABEL: abd_ext_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: subs w8, w8, w1, uxth
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%aext = zext i16 %a to i64
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%bext = zext i16 %b to i64
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%sub = sub i64 %aext, %bext
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%abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
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%trunc = trunc i64 %abs to i16
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ret i16 %trunc
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}
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define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
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; CHECK-LABEL: abd_ext_i16_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: subs w8, w8, w1
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; CHECK-NEXT: cneg w0, w8, ls
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; CHECK-NEXT: ret
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%aext = zext i16 %a to i64
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%bext = zext i32 %b to i64
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%sub = sub i64 %aext, %bext
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%abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
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%trunc = trunc i64 %abs to i16
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ret i16 %trunc
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}
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define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
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; CHECK-LABEL: abd_ext_i16_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: subs w8, w8, w1, uxth
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%aext = zext i16 %a to i64
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%bext = zext i16 %b to i64
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%sub = sub i64 %aext, %bext
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%abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
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%trunc = trunc i64 %abs to i16
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ret i16 %trunc
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}
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define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: abd_ext_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs w8, w0, w1
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; CHECK-NEXT: cneg w0, w8, ls
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; CHECK-NEXT: ret
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%aext = zext i32 %a to i64
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%bext = zext i32 %b to i64
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%sub = sub i64 %aext, %bext
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%abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
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%trunc = trunc i64 %abs to i32
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ret i32 %trunc
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}
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define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
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; CHECK-LABEL: abd_ext_i32_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs w8, w0, w1, uxth
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; CHECK-NEXT: cneg w0, w8, ls
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; CHECK-NEXT: ret
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%aext = zext i32 %a to i64
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%bext = zext i16 %b to i64
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%sub = sub i64 %aext, %bext
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%abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
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%trunc = trunc i64 %abs to i32
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ret i32 %trunc
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}
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define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: abd_ext_i32_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs w8, w0, w1
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; CHECK-NEXT: cneg w0, w8, ls
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; CHECK-NEXT: ret
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%aext = zext i32 %a to i64
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%bext = zext i32 %b to i64
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%sub = sub i64 %aext, %bext
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%abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
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%trunc = trunc i64 %abs to i32
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ret i32 %trunc
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}
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define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: abd_ext_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x1
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; CHECK-NEXT: cneg x0, x8, ls
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; CHECK-NEXT: ret
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%aext = zext i64 %a to i128
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%bext = zext i64 %b to i128
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%sub = sub i128 %aext, %bext
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%abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
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%trunc = trunc i128 %abs to i64
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ret i64 %trunc
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}
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define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: abd_ext_i64_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x1
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; CHECK-NEXT: cneg x0, x8, ls
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; CHECK-NEXT: ret
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%aext = zext i64 %a to i128
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%bext = zext i64 %b to i128
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%sub = sub i128 %aext, %bext
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%abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)
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%trunc = trunc i128 %abs to i64
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ret i64 %trunc
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}
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define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
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; CHECK-LABEL: abd_ext_i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x2
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; CHECK-NEXT: sbc x9, x1, x3
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; CHECK-NEXT: subs x10, x2, x0
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; CHECK-NEXT: sbcs x11, x3, x1
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; CHECK-NEXT: csel x0, x8, x10, lo
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; CHECK-NEXT: csel x1, x9, x11, lo
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; CHECK-NEXT: ret
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%aext = zext i128 %a to i256
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%bext = zext i128 %b to i256
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%sub = sub i256 %aext, %bext
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%abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)
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%trunc = trunc i256 %abs to i128
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ret i128 %trunc
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}
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define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
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; CHECK-LABEL: abd_ext_i128_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x2
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; CHECK-NEXT: sbc x9, x1, x3
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; CHECK-NEXT: subs x10, x2, x0
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; CHECK-NEXT: sbcs x11, x3, x1
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; CHECK-NEXT: csel x0, x8, x10, lo
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; CHECK-NEXT: csel x1, x9, x11, lo
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; CHECK-NEXT: ret
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%aext = zext i128 %a to i256
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%bext = zext i128 %b to i256
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%sub = sub i256 %aext, %bext
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%abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)
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%trunc = trunc i256 %abs to i128
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ret i128 %trunc
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}
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;
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; sub(umax(a,b),umin(a,b)) -> abdu(a,b)
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;
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define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: abd_minmax_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: subs w8, w8, w1, uxtb
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
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%max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
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%sub = sub i8 %max, %min
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ret i8 %sub
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}
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define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
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; CHECK-LABEL: abd_minmax_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: subs w8, w8, w1, uxth
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
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%max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
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%sub = sub i16 %max, %min
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ret i16 %sub
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}
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define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: abd_minmax_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs w8, w0, w1
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; CHECK-NEXT: cneg w0, w8, ls
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; CHECK-NEXT: ret
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%min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
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%max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
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%sub = sub i32 %max, %min
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ret i32 %sub
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}
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define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: abd_minmax_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x1
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; CHECK-NEXT: cneg x0, x8, ls
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; CHECK-NEXT: ret
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%min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
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%max = call i64 @llvm.umax.i64(i64 %a, i64 %b)
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%sub = sub i64 %max, %min
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ret i64 %sub
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}
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define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
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; CHECK-LABEL: abd_minmax_i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x2
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; CHECK-NEXT: sbc x9, x1, x3
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; CHECK-NEXT: subs x10, x2, x0
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; CHECK-NEXT: sbcs x11, x3, x1
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; CHECK-NEXT: csel x0, x8, x10, lo
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; CHECK-NEXT: csel x1, x9, x11, lo
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; CHECK-NEXT: ret
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%min = call i128 @llvm.umin.i128(i128 %a, i128 %b)
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%max = call i128 @llvm.umax.i128(i128 %a, i128 %b)
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%sub = sub i128 %max, %min
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ret i128 %sub
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}
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;
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; select(icmp(a,b),sub(a,b),sub(b,a)) -> abdu(a,b)
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;
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define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: abd_cmp_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: subs w8, w8, w1, uxtb
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%cmp = icmp ugt i8 %a, %b
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%ab = sub i8 %a, %b
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%ba = sub i8 %b, %a
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%sel = select i1 %cmp, i8 %ab, i8 %ba
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ret i8 %sel
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}
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define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
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; CHECK-LABEL: abd_cmp_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: subs w8, w8, w1, uxth
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%cmp = icmp uge i16 %a, %b
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%ab = sub i16 %a, %b
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%ba = sub i16 %b, %a
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%sel = select i1 %cmp, i16 %ab, i16 %ba
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ret i16 %sel
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}
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define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: abd_cmp_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs w8, w0, w1
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; CHECK-NEXT: cneg w0, w8, ls
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; CHECK-NEXT: ret
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%cmp = icmp ult i32 %a, %b
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%ab = sub i32 %a, %b
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%ba = sub i32 %b, %a
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%sel = select i1 %cmp, i32 %ba, i32 %ab
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ret i32 %sel
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}
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define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: abd_cmp_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x1
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; CHECK-NEXT: cneg x0, x8, ls
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; CHECK-NEXT: ret
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%cmp = icmp uge i64 %a, %b
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%ab = sub i64 %a, %b
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%ba = sub i64 %b, %a
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%sel = select i1 %cmp, i64 %ab, i64 %ba
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ret i64 %sel
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}
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define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
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; CHECK-LABEL: abd_cmp_i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: subs x8, x0, x2
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; CHECK-NEXT: sbc x9, x1, x3
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; CHECK-NEXT: subs x10, x2, x0
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; CHECK-NEXT: sbcs x11, x3, x1
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; CHECK-NEXT: csel x0, x8, x10, lo
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; CHECK-NEXT: csel x1, x9, x11, lo
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; CHECK-NEXT: ret
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%cmp = icmp uge i128 %a, %b
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%ab = sub i128 %a, %b
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%ba = sub i128 %b, %a
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%sel = select i1 %cmp, i128 %ab, i128 %ba
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ret i128 %sel
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}
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;
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; negative tests
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;
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define i64 @vector_legalized(i16 %a, i16 %b) {
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; CHECK-LABEL: vector_legalized:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: subs w8, w8, w1, uxth
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; CHECK-NEXT: cneg w0, w8, mi
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; CHECK-NEXT: ret
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%ea = zext i16 %a to i32
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%eb = zext i16 %b to i32
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%s = sub i32 %ea, %eb
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%ab = call i32 @llvm.abs.i32(i32 %s, i1 false)
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%e = zext i32 %ab to i64
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%red = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> zeroinitializer)
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%z = add i64 %red, %e
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ret i64 %z
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}
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;
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; sub(select(icmp(a,b),a,b),select(icmp(a,b),b,a)) -> abdu(a,b)
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;
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|
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define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
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; CHECK-LABEL: abd_select_i8:
|
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; CHECK: // %bb.0:
|
|
; CHECK-NEXT: and w8, w0, #0xff
|
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; CHECK-NEXT: subs w8, w8, w1, uxtb
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; CHECK-NEXT: cneg w0, w8, mi
|
|
; CHECK-NEXT: ret
|
|
%cmp = icmp ult i8 %a, %b
|
|
%ab = select i1 %cmp, i8 %a, i8 %b
|
|
%ba = select i1 %cmp, i8 %b, i8 %a
|
|
%sub = sub i8 %ba, %ab
|
|
ret i8 %sub
|
|
}
|
|
|
|
define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
|
|
; CHECK-LABEL: abd_select_i16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: and w8, w0, #0xffff
|
|
; CHECK-NEXT: subs w8, w8, w1, uxth
|
|
; CHECK-NEXT: cneg w0, w8, mi
|
|
; CHECK-NEXT: ret
|
|
%cmp = icmp ule i16 %a, %b
|
|
%ab = select i1 %cmp, i16 %a, i16 %b
|
|
%ba = select i1 %cmp, i16 %b, i16 %a
|
|
%sub = sub i16 %ba, %ab
|
|
ret i16 %sub
|
|
}
|
|
|
|
define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
|
|
; CHECK-LABEL: abd_select_i32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: subs w8, w0, w1
|
|
; CHECK-NEXT: cneg w0, w8, ls
|
|
; CHECK-NEXT: ret
|
|
%cmp = icmp ugt i32 %a, %b
|
|
%ab = select i1 %cmp, i32 %a, i32 %b
|
|
%ba = select i1 %cmp, i32 %b, i32 %a
|
|
%sub = sub i32 %ab, %ba
|
|
ret i32 %sub
|
|
}
|
|
|
|
define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
|
|
; CHECK-LABEL: abd_select_i64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: subs x8, x0, x1
|
|
; CHECK-NEXT: cneg x0, x8, ls
|
|
; CHECK-NEXT: ret
|
|
%cmp = icmp uge i64 %a, %b
|
|
%ab = select i1 %cmp, i64 %a, i64 %b
|
|
%ba = select i1 %cmp, i64 %b, i64 %a
|
|
%sub = sub i64 %ab, %ba
|
|
ret i64 %sub
|
|
}
|
|
|
|
define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
|
|
; CHECK-LABEL: abd_select_i128:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: subs x8, x0, x2
|
|
; CHECK-NEXT: sbc x9, x1, x3
|
|
; CHECK-NEXT: subs x10, x2, x0
|
|
; CHECK-NEXT: sbcs x11, x3, x1
|
|
; CHECK-NEXT: csel x0, x8, x10, lo
|
|
; CHECK-NEXT: csel x1, x9, x11, lo
|
|
; CHECK-NEXT: ret
|
|
%cmp = icmp ult i128 %a, %b
|
|
%ab = select i1 %cmp, i128 %a, i128 %b
|
|
%ba = select i1 %cmp, i128 %b, i128 %a
|
|
%sub = sub i128 %ba, %ab
|
|
ret i128 %sub
|
|
}
|
|
|
|
declare i8 @llvm.abs.i8(i8, i1)
|
|
declare i16 @llvm.abs.i16(i16, i1)
|
|
declare i32 @llvm.abs.i32(i32, i1)
|
|
declare i64 @llvm.abs.i64(i64, i1)
|
|
declare i128 @llvm.abs.i128(i128, i1)
|
|
|
|
declare i8 @llvm.umax.i8(i8, i8)
|
|
declare i16 @llvm.umax.i16(i16, i16)
|
|
declare i32 @llvm.umax.i32(i32, i32)
|
|
declare i64 @llvm.umax.i64(i64, i64)
|
|
|
|
declare i8 @llvm.umin.i8(i8, i8)
|
|
declare i16 @llvm.umin.i16(i16, i16)
|
|
declare i32 @llvm.umin.i32(i32, i32)
|
|
declare i64 @llvm.umin.i64(i64, i64)
|