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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/addp-shuffle.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

933 lines
38 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16,CHECK-NOFP16-SD
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD
; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16,CHECK-NOFP16-GI
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI
define <4 x i32> @deinterleave_shuffle_v8i32(<8 x i32> %a) {
; CHECK-LABEL: deinterleave_shuffle_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%r0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = add <4 x i32> %r0, %r1
ret <4 x i32> %o
}
define <4 x i32> @deinterleave_shuffle_v8i32_c(<8 x i32> %a) {
; CHECK-LABEL: deinterleave_shuffle_v8i32_c:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%r0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = add <4 x i32> %r1, %r0
ret <4 x i32> %o
}
define <2 x i32> @deinterleave_shuffle_v4i32(<4 x i32> %a) {
; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v4i32:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: addp v0.4s, v0.4s, v0.4s
; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v4i32:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: addp v0.4s, v0.4s, v0.4s
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v4i32:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: uzp1 v1.4s, v0.4s, v0.4s
; CHECK-NOFP16-GI-NEXT: uzp2 v0.4s, v0.4s, v0.4s
; CHECK-NOFP16-GI-NEXT: add v0.2s, v1.2s, v0.2s
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v4i32:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: uzp1 v1.4s, v0.4s, v0.4s
; CHECK-FP16-GI-NEXT: uzp2 v0.4s, v0.4s, v0.4s
; CHECK-FP16-GI-NEXT: add v0.2s, v1.2s, v0.2s
; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%r1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
%o = add <2 x i32> %r0, %r1
ret <2 x i32> %o
}
define <8 x i16> @deinterleave_shuffle_v16i16(<16 x i16> %a) {
; CHECK-LABEL: deinterleave_shuffle_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
%r0 = shufflevector <16 x i16> %a, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x i16> %a, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%o = add <8 x i16> %r0, %r1
ret <8 x i16> %o
}
define <4 x i16> @deinterleave_shuffle_v8i16(<8 x i16> %a) {
; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v8i16:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: addp v0.8h, v0.8h, v0.8h
; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v8i16:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: addp v0.8h, v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v8i16:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: uzp1 v1.8h, v0.8h, v0.8h
; CHECK-NOFP16-GI-NEXT: uzp2 v0.8h, v0.8h, v0.8h
; CHECK-NOFP16-GI-NEXT: add v0.4h, v1.4h, v0.4h
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v8i16:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: uzp1 v1.8h, v0.8h, v0.8h
; CHECK-FP16-GI-NEXT: uzp2 v0.8h, v0.8h, v0.8h
; CHECK-FP16-GI-NEXT: add v0.4h, v1.4h, v0.4h
; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = add <4 x i16> %r0, %r1
ret <4 x i16> %o
}
define <16 x i8> @deinterleave_shuffle_v32i8(<32 x i8> %a) {
; CHECK-LABEL: deinterleave_shuffle_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%r0 = shufflevector <32 x i8> %a, <32 x i8> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%r1 = shufflevector <32 x i8> %a, <32 x i8> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%o = add <16 x i8> %r0, %r1
ret <16 x i8> %o
}
define <8 x i8> @deinterleave_shuffle_v16i8(<16 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v16i8:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: addp v0.16b, v0.16b, v0.16b
; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v16i8:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: addp v0.16b, v0.16b, v0.16b
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v16i8:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: uzp1 v1.16b, v0.16b, v0.16b
; CHECK-NOFP16-GI-NEXT: uzp2 v0.16b, v0.16b, v0.16b
; CHECK-NOFP16-GI-NEXT: add v0.8b, v1.8b, v0.8b
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v16i8:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: uzp1 v1.16b, v0.16b, v0.16b
; CHECK-FP16-GI-NEXT: uzp2 v0.16b, v0.16b, v0.16b
; CHECK-FP16-GI-NEXT: add v0.8b, v1.8b, v0.8b
; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%o = add <8 x i8> %r0, %r1
ret <8 x i8> %o
}
define <4 x i64> @deinterleave_shuffle_v8i64(<8 x i64> %a) {
; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v8i64:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: addp v2.2d, v2.2d, v3.2d
; CHECK-NOFP16-SD-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-NOFP16-SD-NEXT: mov v1.16b, v2.16b
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v8i64:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: addp v2.2d, v2.2d, v3.2d
; CHECK-FP16-SD-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-FP16-SD-NEXT: mov v1.16b, v2.16b
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v8i64:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-NOFP16-GI-NEXT: addp v1.2d, v2.2d, v3.2d
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v8i64:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-FP16-GI-NEXT: addp v1.2d, v2.2d, v3.2d
; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = add <4 x i64> %r0, %r1
ret <4 x i64> %o
}
define <4 x float> @deinterleave_shuffle_v8f32(<8 x float> %a) {
; CHECK-LABEL: deinterleave_shuffle_v8f32:
; CHECK: // %bb.0:
; CHECK-NEXT: faddp v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%r0 = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = fadd <4 x float> %r0, %r1
ret <4 x float> %o
}
define <4 x float> @deinterleave_shuffle_v8f32_c(<8 x float> %a) {
; CHECK-LABEL: deinterleave_shuffle_v8f32_c:
; CHECK: // %bb.0:
; CHECK-NEXT: faddp v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%r0 = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = fadd <4 x float> %r1, %r0
ret <4 x float> %o
}
define <8 x half> @deinterleave_shuffle_v16f16(<16 x half> %a) {
; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v16f16:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: uzp1 v2.8h, v0.8h, v1.8h
; CHECK-NOFP16-SD-NEXT: uzp2 v0.8h, v0.8h, v1.8h
; CHECK-NOFP16-SD-NEXT: fcvtl v1.4s, v0.4h
; CHECK-NOFP16-SD-NEXT: fcvtl v3.4s, v2.4h
; CHECK-NOFP16-SD-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-NOFP16-SD-NEXT: fcvtl2 v2.4s, v2.8h
; CHECK-NOFP16-SD-NEXT: fadd v1.4s, v3.4s, v1.4s
; CHECK-NOFP16-SD-NEXT: fadd v2.4s, v2.4s, v0.4s
; CHECK-NOFP16-SD-NEXT: fcvtn v0.4h, v1.4s
; CHECK-NOFP16-SD-NEXT: fcvtn2 v0.8h, v2.4s
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-LABEL: deinterleave_shuffle_v16f16:
; CHECK-FP16: // %bb.0:
; CHECK-FP16-NEXT: faddp v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v16f16:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: uzp1 v2.8h, v0.8h, v1.8h
; CHECK-NOFP16-GI-NEXT: uzp2 v0.8h, v0.8h, v1.8h
; CHECK-NOFP16-GI-NEXT: fcvtl v1.4s, v2.4h
; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v0.4h
; CHECK-NOFP16-GI-NEXT: fcvtl2 v2.4s, v2.8h
; CHECK-NOFP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-NOFP16-GI-NEXT: fadd v1.4s, v1.4s, v3.4s
; CHECK-NOFP16-GI-NEXT: fadd v2.4s, v2.4s, v0.4s
; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v1.4s
; CHECK-NOFP16-GI-NEXT: fcvtn2 v0.8h, v2.4s
; CHECK-NOFP16-GI-NEXT: ret
%r0 = shufflevector <16 x half> %a, <16 x half> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x half> %a, <16 x half> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%o = fadd <8 x half> %r0, %r1
ret <8 x half> %o
}
define <4 x double> @deinterleave_shuffle_v8f64(<8 x double> %a) {
; CHECK-NOFP16-SD-LABEL: deinterleave_shuffle_v8f64:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: faddp v2.2d, v2.2d, v3.2d
; CHECK-NOFP16-SD-NEXT: faddp v0.2d, v0.2d, v1.2d
; CHECK-NOFP16-SD-NEXT: mov v1.16b, v2.16b
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: deinterleave_shuffle_v8f64:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: faddp v2.2d, v2.2d, v3.2d
; CHECK-FP16-SD-NEXT: faddp v0.2d, v0.2d, v1.2d
; CHECK-FP16-SD-NEXT: mov v1.16b, v2.16b
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: deinterleave_shuffle_v8f64:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: faddp v0.2d, v0.2d, v1.2d
; CHECK-NOFP16-GI-NEXT: faddp v1.2d, v2.2d, v3.2d
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: deinterleave_shuffle_v8f64:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: faddp v0.2d, v0.2d, v1.2d
; CHECK-FP16-GI-NEXT: faddp v1.2d, v2.2d, v3.2d
; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x double> %a, <8 x double> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x double> %a, <8 x double> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = fadd <4 x double> %r0, %r1
ret <4 x double> %o
}
define <4 x i32> @udot(<4 x i32> %z, <16 x i8> %a, <16 x i8> %b) {
; CHECK-NOFP16-SD-LABEL: udot:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: umull v3.8h, v1.8b, v2.8b
; CHECK-NOFP16-SD-NEXT: umull2 v1.8h, v1.16b, v2.16b
; CHECK-NOFP16-SD-NEXT: uaddlp v1.4s, v1.8h
; CHECK-NOFP16-SD-NEXT: uaddlp v2.4s, v3.8h
; CHECK-NOFP16-SD-NEXT: addp v1.4s, v2.4s, v1.4s
; CHECK-NOFP16-SD-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: udot:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: umull v3.8h, v1.8b, v2.8b
; CHECK-FP16-SD-NEXT: umull2 v1.8h, v1.16b, v2.16b
; CHECK-FP16-SD-NEXT: uaddlp v1.4s, v1.8h
; CHECK-FP16-SD-NEXT: uaddlp v2.4s, v3.8h
; CHECK-FP16-SD-NEXT: addp v1.4s, v2.4s, v1.4s
; CHECK-FP16-SD-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: udot:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: umull v3.8h, v1.8b, v2.8b
; CHECK-NOFP16-GI-NEXT: umull2 v1.8h, v1.16b, v2.16b
; CHECK-NOFP16-GI-NEXT: uaddlp v2.4s, v3.8h
; CHECK-NOFP16-GI-NEXT: uaddlp v1.4s, v1.8h
; CHECK-NOFP16-GI-NEXT: addp v1.4s, v2.4s, v1.4s
; CHECK-NOFP16-GI-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: udot:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: umull v3.8h, v1.8b, v2.8b
; CHECK-FP16-GI-NEXT: umull2 v1.8h, v1.16b, v2.16b
; CHECK-FP16-GI-NEXT: uaddlp v2.4s, v3.8h
; CHECK-FP16-GI-NEXT: uaddlp v1.4s, v1.8h
; CHECK-FP16-GI-NEXT: addp v1.4s, v2.4s, v1.4s
; CHECK-FP16-GI-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-FP16-GI-NEXT: ret
%za = zext <16 x i8> %a to <16 x i32>
%zb = zext <16 x i8> %b to <16 x i32>
%m = mul <16 x i32> %za, %zb
%r0 = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%m2 = add <8 x i32> %r0, %r1
%s0 = shufflevector <8 x i32> %m2, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%s1 = shufflevector <8 x i32> %m2, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = add <4 x i32> %s0, %s1
%n = add <4 x i32> %z, %o
ret <4 x i32> %n
}
define <4 x i32> @sdot(<4 x i32> %z, <16 x i8> %a, <16 x i8> %b) {
; CHECK-NOFP16-SD-LABEL: sdot:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: smull v3.8h, v1.8b, v2.8b
; CHECK-NOFP16-SD-NEXT: smull2 v1.8h, v1.16b, v2.16b
; CHECK-NOFP16-SD-NEXT: saddlp v1.4s, v1.8h
; CHECK-NOFP16-SD-NEXT: saddlp v2.4s, v3.8h
; CHECK-NOFP16-SD-NEXT: addp v1.4s, v2.4s, v1.4s
; CHECK-NOFP16-SD-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: sdot:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: smull v3.8h, v1.8b, v2.8b
; CHECK-FP16-SD-NEXT: smull2 v1.8h, v1.16b, v2.16b
; CHECK-FP16-SD-NEXT: saddlp v1.4s, v1.8h
; CHECK-FP16-SD-NEXT: saddlp v2.4s, v3.8h
; CHECK-FP16-SD-NEXT: addp v1.4s, v2.4s, v1.4s
; CHECK-FP16-SD-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: sdot:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: smull v3.8h, v1.8b, v2.8b
; CHECK-NOFP16-GI-NEXT: smull2 v1.8h, v1.16b, v2.16b
; CHECK-NOFP16-GI-NEXT: saddlp v2.4s, v3.8h
; CHECK-NOFP16-GI-NEXT: saddlp v1.4s, v1.8h
; CHECK-NOFP16-GI-NEXT: addp v1.4s, v2.4s, v1.4s
; CHECK-NOFP16-GI-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: sdot:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: smull v3.8h, v1.8b, v2.8b
; CHECK-FP16-GI-NEXT: smull2 v1.8h, v1.16b, v2.16b
; CHECK-FP16-GI-NEXT: saddlp v2.4s, v3.8h
; CHECK-FP16-GI-NEXT: saddlp v1.4s, v1.8h
; CHECK-FP16-GI-NEXT: addp v1.4s, v2.4s, v1.4s
; CHECK-FP16-GI-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-FP16-GI-NEXT: ret
%za = sext <16 x i8> %a to <16 x i32>
%zb = sext <16 x i8> %b to <16 x i32>
%m = mul <16 x i32> %za, %zb
%r0 = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%m2 = add <8 x i32> %r0, %r1
%s0 = shufflevector <8 x i32> %m2, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%s1 = shufflevector <8 x i32> %m2, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = add <4 x i32> %s0, %s1
%n = add <4 x i32> %z, %o
ret <4 x i32> %n
}
define <8 x i8> @manual_addp_v8i8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: manual_addp_v8i8:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
start:
%0 = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%1 = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%2 = add <8 x i8> %0, %1
ret <8 x i8> %2
}
define <4 x i16> @manual_addp_v4i16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: manual_addp_v4i16:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret
start:
%0 = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%1 = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%2 = add <4 x i16> %0, %1
ret <4 x i16> %2
}
define <2 x i32> @manual_addp_v2i32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: manual_addp_v2i32:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret
start:
%0 = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2>
%1 = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3>
%2 = add <2 x i32> %0, %1
ret <2 x i32> %2
}
define <16 x i8> @manual_addp_v16i8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: manual_addp_v16i8:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%1 = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%2 = add <16 x i8> %0, %1
ret <16 x i8> %2
}
define <8 x i16> @manual_addp_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: manual_addp_v8i16:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
start:
%0 = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%1 = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%2 = add <8 x i16> %0, %1
ret <8 x i16> %2
}
define <4 x i32> @manual_addp_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: manual_addp_v4i32:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
start:
%0 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%2 = add <4 x i32> %0, %1
ret <4 x i32> %2
}
define <2 x i64> @manual_addp_v2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: manual_addp_v2i64:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret
start:
%0 = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
%1 = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
%2 = add <2 x i64> %0, %1
ret <2 x i64> %2
}
define <8 x half> @manual_faddp_v8f16(<8 x half> %a, <8 x half> %b) {
; CHECK-NOFP16-SD-LABEL: manual_faddp_v8f16:
; CHECK-NOFP16-SD: // %bb.0: // %start
; CHECK-NOFP16-SD-NEXT: uzp1 v2.8h, v0.8h, v1.8h
; CHECK-NOFP16-SD-NEXT: uzp2 v0.8h, v0.8h, v1.8h
; CHECK-NOFP16-SD-NEXT: fcvtl v1.4s, v0.4h
; CHECK-NOFP16-SD-NEXT: fcvtl v3.4s, v2.4h
; CHECK-NOFP16-SD-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-NOFP16-SD-NEXT: fcvtl2 v2.4s, v2.8h
; CHECK-NOFP16-SD-NEXT: fadd v1.4s, v3.4s, v1.4s
; CHECK-NOFP16-SD-NEXT: fadd v2.4s, v2.4s, v0.4s
; CHECK-NOFP16-SD-NEXT: fcvtn v0.4h, v1.4s
; CHECK-NOFP16-SD-NEXT: fcvtn2 v0.8h, v2.4s
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-LABEL: manual_faddp_v8f16:
; CHECK-FP16: // %bb.0: // %start
; CHECK-FP16-NEXT: faddp v0.8h, v0.8h, v1.8h
; CHECK-FP16-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: manual_faddp_v8f16:
; CHECK-NOFP16-GI: // %bb.0: // %start
; CHECK-NOFP16-GI-NEXT: uzp1 v2.8h, v0.8h, v1.8h
; CHECK-NOFP16-GI-NEXT: uzp2 v0.8h, v0.8h, v1.8h
; CHECK-NOFP16-GI-NEXT: fcvtl v1.4s, v2.4h
; CHECK-NOFP16-GI-NEXT: fcvtl v3.4s, v0.4h
; CHECK-NOFP16-GI-NEXT: fcvtl2 v2.4s, v2.8h
; CHECK-NOFP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-NOFP16-GI-NEXT: fadd v1.4s, v1.4s, v3.4s
; CHECK-NOFP16-GI-NEXT: fadd v2.4s, v2.4s, v0.4s
; CHECK-NOFP16-GI-NEXT: fcvtn v0.4h, v1.4s
; CHECK-NOFP16-GI-NEXT: fcvtn2 v0.8h, v2.4s
; CHECK-NOFP16-GI-NEXT: ret
start:
%0 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%1 = shufflevector <8 x half> %a, <8 x half> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%2 = fadd <8 x half> %0, %1
ret <8 x half> %2
}
define <2 x float> @manual_faddp_v2f32(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: manual_faddp_v2f32:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: faddp v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret
start:
%0 = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 0, i32 2>
%1 = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 3>
%2 = fadd <2 x float> %0, %1
ret <2 x float> %2
}
define i64 @addp_2xi64(<2 x i64> %a) {
; CHECK-NOFP16-SD-LABEL: addp_2xi64:
; CHECK-NOFP16-SD: // %bb.0: // %entry
; CHECK-NOFP16-SD-NEXT: addp d0, v0.2d
; CHECK-NOFP16-SD-NEXT: fmov x0, d0
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: addp_2xi64:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: addp d0, v0.2d
; CHECK-FP16-SD-NEXT: fmov x0, d0
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: addp_2xi64:
; CHECK-NOFP16-GI: // %bb.0: // %entry
; CHECK-NOFP16-GI-NEXT: dup v1.2d, v0.d[1]
; CHECK-NOFP16-GI-NEXT: add v0.2d, v0.2d, v1.2d
; CHECK-NOFP16-GI-NEXT: fmov x0, d0
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: addp_2xi64:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: dup v1.2d, v0.d[1]
; CHECK-FP16-GI-NEXT: add v0.2d, v0.2d, v1.2d
; CHECK-FP16-GI-NEXT: fmov x0, d0
; CHECK-FP16-GI-NEXT: ret
entry:
%shift = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%0 = add <2 x i64> %a, %shift
%1 = extractelement <2 x i64> %0, i32 0
ret i64 %1
}
define i64 @addp_2xi64_commute(<2 x i64> %a) {
; CHECK-NOFP16-SD-LABEL: addp_2xi64_commute:
; CHECK-NOFP16-SD: // %bb.0: // %entry
; CHECK-NOFP16-SD-NEXT: addp d0, v0.2d
; CHECK-NOFP16-SD-NEXT: fmov x0, d0
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: addp_2xi64_commute:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: addp d0, v0.2d
; CHECK-FP16-SD-NEXT: fmov x0, d0
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: addp_2xi64_commute:
; CHECK-NOFP16-GI: // %bb.0: // %entry
; CHECK-NOFP16-GI-NEXT: dup v1.2d, v0.d[1]
; CHECK-NOFP16-GI-NEXT: add v0.2d, v1.2d, v0.2d
; CHECK-NOFP16-GI-NEXT: fmov x0, d0
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: addp_2xi64_commute:
; CHECK-FP16-GI: // %bb.0: // %entry
; CHECK-FP16-GI-NEXT: dup v1.2d, v0.d[1]
; CHECK-FP16-GI-NEXT: add v0.2d, v1.2d, v0.2d
; CHECK-FP16-GI-NEXT: fmov x0, d0
; CHECK-FP16-GI-NEXT: ret
entry:
%shift = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%0 = add <2 x i64> %shift, %a
%1 = extractelement <2 x i64> %0, i32 0
ret i64 %1
}
define <4 x i32> @or_deinterleave_shuffle_v8i32(<8 x i32> %a) {
; CHECK-LABEL: or_deinterleave_shuffle_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%r0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = or disjoint <4 x i32> %r0, %r1
ret <4 x i32> %o
}
define <4 x i32> @or_deinterleave_shuffle_v8i32_c(<8 x i32> %a) {
; CHECK-LABEL: or_deinterleave_shuffle_v8i32_c:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%r0 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = or disjoint <4 x i32> %r1, %r0
ret <4 x i32> %o
}
define <2 x i32> @or_deinterleave_shuffle_v4i32(<4 x i32> %a) {
; CHECK-NOFP16-SD-LABEL: or_deinterleave_shuffle_v4i32:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: addp v0.4s, v0.4s, v0.4s
; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: or_deinterleave_shuffle_v4i32:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: addp v0.4s, v0.4s, v0.4s
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: or_deinterleave_shuffle_v4i32:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: uzp1 v1.4s, v0.4s, v0.4s
; CHECK-NOFP16-GI-NEXT: uzp2 v0.4s, v0.4s, v0.4s
; CHECK-NOFP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: or_deinterleave_shuffle_v4i32:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: uzp1 v1.4s, v0.4s, v0.4s
; CHECK-FP16-GI-NEXT: uzp2 v0.4s, v0.4s, v0.4s
; CHECK-FP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%r1 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
%o = or disjoint <2 x i32> %r0, %r1
ret <2 x i32> %o
}
define <8 x i16> @or_deinterleave_shuffle_v16i16(<16 x i16> %a) {
; CHECK-LABEL: or_deinterleave_shuffle_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
%r0 = shufflevector <16 x i16> %a, <16 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x i16> %a, <16 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%o = or disjoint <8 x i16> %r0, %r1
ret <8 x i16> %o
}
define <4 x i16> @or_deinterleave_shuffle_v8i16(<8 x i16> %a) {
; CHECK-NOFP16-SD-LABEL: or_deinterleave_shuffle_v8i16:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: addp v0.8h, v0.8h, v0.8h
; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: or_deinterleave_shuffle_v8i16:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: addp v0.8h, v0.8h, v0.8h
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: or_deinterleave_shuffle_v8i16:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: uzp1 v1.8h, v0.8h, v0.8h
; CHECK-NOFP16-GI-NEXT: uzp2 v0.8h, v0.8h, v0.8h
; CHECK-NOFP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: or_deinterleave_shuffle_v8i16:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: uzp1 v1.8h, v0.8h, v0.8h
; CHECK-FP16-GI-NEXT: uzp2 v0.8h, v0.8h, v0.8h
; CHECK-FP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = or disjoint <4 x i16> %r0, %r1
ret <4 x i16> %o
}
define <16 x i8> @or_deinterleave_shuffle_v32i8(<32 x i8> %a) {
; CHECK-LABEL: or_deinterleave_shuffle_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
%r0 = shufflevector <32 x i8> %a, <32 x i8> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%r1 = shufflevector <32 x i8> %a, <32 x i8> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%o = or disjoint <16 x i8> %r0, %r1
ret <16 x i8> %o
}
define <8 x i8> @or_deinterleave_shuffle_v16i8(<16 x i8> %a) {
; CHECK-NOFP16-SD-LABEL: or_deinterleave_shuffle_v16i8:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: addp v0.16b, v0.16b, v0.16b
; CHECK-NOFP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: or_deinterleave_shuffle_v16i8:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: addp v0.16b, v0.16b, v0.16b
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: or_deinterleave_shuffle_v16i8:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: uzp1 v1.16b, v0.16b, v0.16b
; CHECK-NOFP16-GI-NEXT: uzp2 v0.16b, v0.16b, v0.16b
; CHECK-NOFP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: or_deinterleave_shuffle_v16i8:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: uzp1 v1.16b, v0.16b, v0.16b
; CHECK-FP16-GI-NEXT: uzp2 v0.16b, v0.16b, v0.16b
; CHECK-FP16-GI-NEXT: orr v0.8b, v1.8b, v0.8b
; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%r1 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%o = or disjoint <8 x i8> %r0, %r1
ret <8 x i8> %o
}
define <4 x i64> @or_deinterleave_shuffle_v8i64(<8 x i64> %a) {
; CHECK-NOFP16-SD-LABEL: or_deinterleave_shuffle_v8i64:
; CHECK-NOFP16-SD: // %bb.0:
; CHECK-NOFP16-SD-NEXT: addp v2.2d, v2.2d, v3.2d
; CHECK-NOFP16-SD-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-NOFP16-SD-NEXT: mov v1.16b, v2.16b
; CHECK-NOFP16-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: or_deinterleave_shuffle_v8i64:
; CHECK-FP16-SD: // %bb.0:
; CHECK-FP16-SD-NEXT: addp v2.2d, v2.2d, v3.2d
; CHECK-FP16-SD-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-FP16-SD-NEXT: mov v1.16b, v2.16b
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-NOFP16-GI-LABEL: or_deinterleave_shuffle_v8i64:
; CHECK-NOFP16-GI: // %bb.0:
; CHECK-NOFP16-GI-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-NOFP16-GI-NEXT: addp v1.2d, v2.2d, v3.2d
; CHECK-NOFP16-GI-NEXT: ret
;
; CHECK-FP16-GI-LABEL: or_deinterleave_shuffle_v8i64:
; CHECK-FP16-GI: // %bb.0:
; CHECK-FP16-GI-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-FP16-GI-NEXT: addp v1.2d, v2.2d, v3.2d
; CHECK-FP16-GI-NEXT: ret
%r0 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%r1 = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%o = or disjoint <4 x i64> %r0, %r1
ret <4 x i64> %o
}
define <8 x i8> @or_manual_addp_v8i8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: or_manual_addp_v8i8:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
start:
%0 = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%1 = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%2 = or disjoint <8 x i8> %0, %1
ret <8 x i8> %2
}
define <4 x i16> @or_manual_addp_v4i16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: or_manual_addp_v4i16:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.4h, v0.4h, v1.4h
; CHECK-NEXT: ret
start:
%0 = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%1 = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%2 = or disjoint <4 x i16> %0, %1
ret <4 x i16> %2
}
define <2 x i32> @or_manual_addp_v2i32(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: or_manual_addp_v2i32:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret
start:
%0 = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2>
%1 = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3>
%2 = or disjoint <2 x i32> %0, %1
ret <2 x i32> %2
}
define <16 x i8> @or_manual_addp_v16i8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: or_manual_addp_v16i8:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%1 = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%2 = or disjoint <16 x i8> %0, %1
ret <16 x i8> %2
}
define <8 x i16> @or_manual_addp_v8i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: or_manual_addp_v8i16:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret
start:
%0 = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%1 = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%2 = or disjoint <8 x i16> %0, %1
ret <8 x i16> %2
}
define <4 x i32> @or_manual_addp_v4i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: or_manual_addp_v4i32:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
start:
%0 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%1 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%2 = or disjoint <4 x i32> %0, %1
ret <4 x i32> %2
}
define <2 x i64> @or_manual_addp_v2i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: or_manual_addp_v2i64:
; CHECK: // %bb.0: // %start
; CHECK-NEXT: addp v0.2d, v0.2d, v1.2d
; CHECK-NEXT: ret
start:
%0 = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2>
%1 = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
%2 = or disjoint <2 x i64> %0, %1
ret <2 x i64> %2
}
define i64 @or_addp_2xi64(<2 x i64> %a) {
; CHECK-LABEL: or_addp_2xi64:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: dup v1.2d, v0.d[1]
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
entry:
%shift = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%0 = or disjoint <2 x i64> %a, %shift
%1 = extractelement <2 x i64> %0, i32 0
ret i64 %1
}
define i64 @or_addp_2xi64_commute(<2 x i64> %a) {
; CHECK-LABEL: or_addp_2xi64_commute:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: dup v1.2d, v0.d[1]
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
entry:
%shift = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 1, i32 undef>
%0 = or disjoint <2 x i64> %shift, %a
%1 = extractelement <2 x i64> %0, i32 0
ret i64 %1
}
define <16 x i8> @xtn_uzp2_v16i8_add(<16 x i8> %x) {
; CHECK-LABEL: xtn_uzp2_v16i8_add:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
; CHECK-NEXT: ret
%e = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
%o = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
%r = add <16 x i8> %e, %o
ret <16 x i8> %r
}
define <16 x i8> @xtn_uzp2_v16i8_or(<16 x i8> %x) {
; CHECK-LABEL: xtn_uzp2_v16i8_or:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.16b, v0.16b, v0.16b
; CHECK-NEXT: ret
%e = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
%o = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
%r = or disjoint <16 x i8> %e, %o
ret <16 x i8> %r
}
define <8 x i16> @xtn_uzp2_v8i16_add(<8 x i16> %x) {
; CHECK-LABEL: xtn_uzp2_v8i16_add:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ret
%e = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 poison, i32 poison, i32 poison>
%o = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
%r = add <8 x i16> %e, %o
ret <8 x i16> %r
}
define <8 x i16> @xtn_uzp2_v8i16_or(<8 x i16> %x) {
; CHECK-LABEL: xtn_uzp2_v8i16_or:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.8h, v0.8h, v0.8h
; CHECK-NEXT: ret
%e = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 poison, i32 poison, i32 poison>
%o = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
%r = or disjoint <8 x i16> %e, %o
ret <8 x i16> %r
}
define <4 x i32> @xtn_uzp2_v4i32_add(<4 x i32> %x) {
; CHECK-LABEL: xtn_uzp2_v4i32_add:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ret
%e = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 0, i32 2, i32 poison, i32 poison>
%o = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 1, i32 3, i32 poison, i32 poison>
%r = add <4 x i32> %e, %o
ret <4 x i32> %r
}
define <4 x i32> @xtn_uzp2_v4i32_or(<4 x i32> %x) {
; CHECK-LABEL: xtn_uzp2_v4i32_or:
; CHECK: // %bb.0:
; CHECK-NEXT: addp v0.4s, v0.4s, v0.4s
; CHECK-NEXT: ret
%e = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 0, i32 2, i32 poison, i32 poison>
%o = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 1, i32 3, i32 poison, i32 poison>
%r = or disjoint <4 x i32> %e, %o
ret <4 x i32> %r
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-NOFP16: {{.*}}
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