derek.holloway
7502bf64a4
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115 lines
3.8 KiB
LLVM
115 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-elf < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-none-elf -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define <2 x i32> @test_v2i64(<2 x i64> %n) {
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; CHECK-SD-LABEL: test_v2i64:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sshr v0.2d, v0.2d, #35
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; CHECK-SD-NEXT: xtn v0.2s, v0.2d
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; CHECK-SD-NEXT: usra v0.2s, v0.2s, #31
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test_v2i64:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: ushr v1.2d, v0.2d, #63
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; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #35
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; CHECK-GI-NEXT: xtn v1.2s, v1.2d
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; CHECK-GI-NEXT: xtn v0.2s, v0.2d
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; CHECK-GI-NEXT: add v0.2s, v1.2s, v0.2s
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; CHECK-GI-NEXT: ret
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entry:
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%shr = lshr <2 x i64> %n, splat (i64 63)
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%vmovn.i4 = trunc nuw nsw <2 x i64> %shr to <2 x i32>
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%shr1 = ashr <2 x i64> %n, splat (i64 35)
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%vmovn.i = trunc nsw <2 x i64> %shr1 to <2 x i32>
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%add = add nsw <2 x i32> %vmovn.i4, %vmovn.i
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ret <2 x i32> %add
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}
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define <4 x i16> @test_v4i32(<4 x i32> %n) {
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; CHECK-SD-LABEL: test_v4i32:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sshr v0.4s, v0.4s, #17
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; CHECK-SD-NEXT: xtn v0.4h, v0.4s
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; CHECK-SD-NEXT: usra v0.4h, v0.4h, #15
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test_v4i32:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: ushr v1.4s, v0.4s, #31
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; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #17
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; CHECK-GI-NEXT: xtn v1.4h, v1.4s
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; CHECK-GI-NEXT: xtn v0.4h, v0.4s
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; CHECK-GI-NEXT: add v0.4h, v1.4h, v0.4h
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; CHECK-GI-NEXT: ret
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entry:
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%shr = lshr <4 x i32> %n, splat (i32 31)
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%vmovn.i4 = trunc nuw nsw <4 x i32> %shr to <4 x i16>
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%shr1 = ashr <4 x i32> %n, splat (i32 17)
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%vmovn.i = trunc nsw <4 x i32> %shr1 to <4 x i16>
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%add = add nsw <4 x i16> %vmovn.i4, %vmovn.i
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ret <4 x i16> %add
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}
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define <8 x i8> @test_v8i16(<8 x i16> %n) {
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; CHECK-SD-LABEL: test_v8i16:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sshr v0.8h, v0.8h, #9
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; CHECK-SD-NEXT: xtn v0.8b, v0.8h
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; CHECK-SD-NEXT: usra v0.8b, v0.8b, #7
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test_v8i16:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: ushr v1.8h, v0.8h, #15
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; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #9
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; CHECK-GI-NEXT: xtn v1.8b, v1.8h
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; CHECK-GI-NEXT: xtn v0.8b, v0.8h
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; CHECK-GI-NEXT: add v0.8b, v1.8b, v0.8b
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; CHECK-GI-NEXT: ret
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entry:
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%shr = lshr <8 x i16> %n, splat (i16 15)
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%vmovn.i4 = trunc nuw nsw <8 x i16> %shr to <8 x i8>
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%shr1 = ashr <8 x i16> %n, splat (i16 9)
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%vmovn.i = trunc nsw <8 x i16> %shr1 to <8 x i8>
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%add = add nsw <8 x i8> %vmovn.i4, %vmovn.i
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ret <8 x i8> %add
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}
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define <2 x i32> @test_v2i64_smallsrl(<2 x i64> %n) {
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; CHECK-LABEL: test_v2i64_smallsrl:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ushr v1.2d, v0.2d, #62
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; CHECK-NEXT: sshr v0.2d, v0.2d, #35
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; CHECK-NEXT: xtn v1.2s, v1.2d
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: add v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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entry:
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%shr = lshr <2 x i64> %n, splat (i64 62)
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%vmovn.i4 = trunc nuw nsw <2 x i64> %shr to <2 x i32>
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%shr1 = ashr <2 x i64> %n, splat (i64 35)
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%vmovn.i = trunc nsw <2 x i64> %shr1 to <2 x i32>
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%add = add nsw <2 x i32> %vmovn.i4, %vmovn.i
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ret <2 x i32> %add
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}
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define <2 x i32> @test_v2i64_smallsra(<2 x i64> %n) {
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; CHECK-LABEL: test_v2i64_smallsra:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ushr v1.2d, v0.2d, #63
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; CHECK-NEXT: shrn v0.2s, v0.2d, #27
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; CHECK-NEXT: xtn v1.2s, v1.2d
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; CHECK-NEXT: add v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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entry:
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%shr = lshr <2 x i64> %n, splat (i64 63)
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%vmovn.i4 = trunc nuw nsw <2 x i64> %shr to <2 x i32>
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%shr1 = ashr <2 x i64> %n, splat (i64 27)
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%vmovn.i = trunc nsw <2 x i64> %shr1 to <2 x i32>
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%add = add nsw <2 x i32> %vmovn.i4, %vmovn.i
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ret <2 x i32> %add
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}
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