derek.holloway
7502bf64a4
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70 lines
2.0 KiB
LLVM
70 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 < %s -aarch64-enable-atomic-cfg-tidy=0 -aarch64-enable-gep-opt=false -verify-machineinstrs | FileCheck %s
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target triple = "arm64-apple-ios"
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; rdar://12462006
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; CSE between "icmp reg reg" and "sub reg reg".
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; Both can be in the same basic block or in different basic blocks.
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define ptr @t1(ptr %base, ptr nocapture %offset, i32 %size) nounwind {
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; CHECK-LABEL: t1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: ldr w8, [x1]
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; CHECK-NEXT: subs w9, w8, w2
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; CHECK-NEXT: b.ge LBB0_2
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; CHECK-NEXT: ; %bb.1:
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB0_2: ; %if.end
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; CHECK-NEXT: add x0, x0, w9, sxtw
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; CHECK-NEXT: sub w8, w8, w9
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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entry:
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%0 = load i32, ptr %offset, align 4
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%cmp = icmp slt i32 %0, %size
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%s = sub nsw i32 %0, %size
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br i1 %cmp, label %return, label %if.end
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if.end:
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%sub = sub nsw i32 %0, %size
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%s2 = sub nsw i32 %s, %size
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%s3 = sub nsw i32 %sub, %s2
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store i32 %s3, ptr %offset, align 4
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%add.ptr = getelementptr inbounds i8, ptr %base, i32 %sub
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br label %return
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return:
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%retval.0 = phi ptr [ %add.ptr, %if.end ], [ null, %entry ]
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ret ptr %retval.0
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}
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; CSE between "icmp reg imm" and "sub reg imm".
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define ptr @t2(ptr %base, ptr nocapture %offset) nounwind {
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; CHECK-LABEL: t2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: ldr w8, [x1]
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; CHECK-NEXT: subs w8, w8, #1
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; CHECK-NEXT: b.lt LBB1_2
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; CHECK-NEXT: ; %bb.1: ; %if.end
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; CHECK-NEXT: add x0, x0, w8, sxtw
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; CHECK-NEXT: str w8, [x1]
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB1_2:
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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entry:
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%0 = load i32, ptr %offset, align 4
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%cmp = icmp slt i32 %0, 1
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br i1 %cmp, label %return, label %if.end
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if.end:
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%sub = sub nsw i32 %0, 1
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store i32 %sub, ptr %offset, align 4
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%add.ptr = getelementptr inbounds i8, ptr %base, i32 %sub
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br label %return
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return:
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%retval.0 = phi ptr [ %add.ptr, %if.end ], [ null, %entry ]
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ret ptr %retval.0
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}
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