derek.holloway
7502bf64a4
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290 lines
8.4 KiB
LLVM
290 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT
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; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFPRCVT
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; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT
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; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFPRCVT
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;
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; Lround
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;
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define float @lround_i32_f16_simd(half %x) {
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; CHECK-FPRCVT-LABEL: lround_i32_f16_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas s0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lround_i32_f16_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas w8, h0
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; CHECK-NOFPRCVT-NEXT: fmov s0, w8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i32 @llvm.lround.i32.f16(half %x)
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%sum = bitcast i32 %val to float
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ret float %sum
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}
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define float @lround_i32_f32_simd(float %x) {
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; CHECK-LABEL: lround_i32_f32_simd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtas s0, s0
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; CHECK-NEXT: ret
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%val = call i32 @llvm.lround.i32.f32(float %x)
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%bc = bitcast i32 %val to float
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ret float %bc
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}
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define float @lround_i32_f64_simd(double %x) {
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; CHECK-FPRCVT-LABEL: lround_i32_f64_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas s0, d0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lround_i32_f64_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas w8, d0
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; CHECK-NOFPRCVT-NEXT: fmov s0, w8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i32 @llvm.lround.i32.f64(double %x)
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%bc = bitcast i32 %val to float
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ret float %bc
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}
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define double @lround_i64_f16_simd(half %x) {
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; CHECK-FPRCVT-LABEL: lround_i64_f16_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas d0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lround_i64_f16_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas x8, h0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.lround.i64.f16(half %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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define double @lround_i64_f32_simd(float %x) {
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; CHECK-FPRCVT-LABEL: lround_i64_f32_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas d0, s0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lround_i64_f32_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas x8, s0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.lround.i64.f32(float %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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define double @lround_i64_f64_simd(double %x) {
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; CHECK-LABEL: lround_i64_f64_simd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtas d0, d0
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; CHECK-NEXT: ret
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%val = call i64 @llvm.lround.i64.f64(double %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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;
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; Llround
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;
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define double @llround_i64_f16_simd(half %x) {
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; CHECK-FPRCVT-LABEL: llround_i64_f16_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas d0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: llround_i64_f16_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas x8, h0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.llround.i64.f16(half %x)
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%sum = bitcast i64 %val to double
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ret double %sum
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}
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define double @llround_i64_f32_simd(float %x) {
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; CHECK-FPRCVT-LABEL: llround_i64_f32_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas d0, s0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: llround_i64_f32_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas x8, s0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.llround.i64.f32(float %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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define double @llround_i64_f64_simd(double %x) {
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; CHECK-LABEL: llround_i64_f64_simd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtas d0, d0
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; CHECK-NEXT: ret
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%val = call i64 @llvm.llround.i64.f64(double %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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;
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; Lrint
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;
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define float @lrint_i32_f16_simd(half %x) {
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; CHECK-FPRCVT-LABEL: lrint_i32_f16_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx h0, h0
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; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lrint_i32_f16_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx h0, h0
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; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h0
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; CHECK-NOFPRCVT-NEXT: fmov s0, w8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i32 @llvm.lrint.i32.f16(half %x)
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%sum = bitcast i32 %val to float
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ret float %sum
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}
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define float @lrint_i32_f32_simd(float %x) {
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; CHECK-LABEL: lrint_i32_f32_simd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintx s0, s0
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; CHECK-NEXT: fcvtzs s0, s0
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; CHECK-NEXT: ret
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%val = call i32 @llvm.lrint.i32.f32(float %x)
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%bc = bitcast i32 %val to float
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ret float %bc
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}
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define float @lrint_i32_f64_simd(double %x) {
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; CHECK-FPRCVT-LABEL: lrint_i32_f64_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx d0, d0
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; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lrint_i32_f64_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx d0, d0
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; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0
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; CHECK-NOFPRCVT-NEXT: fmov s0, w8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i32 @llvm.lrint.i32.f64(double %x)
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%bc = bitcast i32 %val to float
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ret float %bc
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}
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define double @lrint_i64_f16_simd(half %x) {
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; CHECK-FPRCVT-LABEL: lrint_i64_f16_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx h0, h0
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; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lrint_i64_f16_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx h0, h0
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; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.lrint.i64.f16(half %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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define double @lrint_i64_f32_simd(float %x) {
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; CHECK-FPRCVT-LABEL: lrint_i64_f32_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx s0, s0
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; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lrint_i64_f32_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx s0, s0
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; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.lrint.i64.f32(float %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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define double @lrint_i64_f64_simd(double %x) {
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; CHECK-LABEL: lrint_i64_f64_simd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintx d0, d0
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; CHECK-NEXT: fcvtzs d0, d0
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; CHECK-NEXT: ret
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%val = call i64 @llvm.lrint.i64.f64(double %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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;
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; Llrint
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;
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define double @llrint_i64_f16_simd(half %x) {
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; CHECK-FPRCVT-LABEL: llrint_i64_f16_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx h0, h0
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; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: llrint_i64_f16_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx h0, h0
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; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.llrint.i64.f16(half %x)
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%sum = bitcast i64 %val to double
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ret double %sum
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}
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define double @llrint_i64_f32_simd(float %x) {
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; CHECK-FPRCVT-LABEL: llrint_i64_f32_simd:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx s0, s0
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; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: llrint_i64_f32_simd:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx s0, s0
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; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.llrint.i64.f32(float %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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define double @llrint_i64_f64_simd(double %x) {
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; CHECK-LABEL: llrint_i64_f64_simd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintx d0, d0
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; CHECK-NEXT: fcvtzs d0, d0
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; CHECK-NEXT: ret
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%val = call i64 @llvm.llrint.i64.f64(double %x)
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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