derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
201 lines
8.4 KiB
LLVM
201 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
|
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
|
|
; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
|
|
|
|
define <8 x i8> @test_vextd(<8 x i8> %tmp1, <8 x i8> %tmp2) {
|
|
; CHECK-LABEL: test_vextd:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #3
|
|
; CHECK-NEXT: ret
|
|
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
|
|
ret <8 x i8> %tmp3
|
|
}
|
|
|
|
define <8 x i8> @test_vextRd(<8 x i8> %tmp1, <8 x i8> %tmp2) {
|
|
; CHECK-LABEL: test_vextRd:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #5
|
|
; CHECK-NEXT: ret
|
|
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
|
|
ret <8 x i8> %tmp3
|
|
}
|
|
|
|
define <16 x i8> @test_vextq(<16 x i8> %tmp1, <16 x i8> %tmp2) {
|
|
; CHECK-LABEL: test_vextq:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #3
|
|
; CHECK-NEXT: ret
|
|
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
|
|
ret <16 x i8> %tmp3
|
|
}
|
|
|
|
define <16 x i8> @test_vextRq(<16 x i8> %tmp1, <16 x i8> %tmp2) {
|
|
; CHECK-LABEL: test_vextRq:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #7
|
|
; CHECK-NEXT: ret
|
|
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
|
|
ret <16 x i8> %tmp3
|
|
}
|
|
|
|
define <4 x i16> @test_vextd16(<4 x i16> %tmp1, <4 x i16> %tmp2) {
|
|
; CHECK-LABEL: test_vextd16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #6
|
|
; CHECK-NEXT: ret
|
|
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
|
|
ret <4 x i16> %tmp3
|
|
}
|
|
|
|
define <4 x i32> @test_vextq32(<4 x i32> %tmp1, <4 x i32> %tmp2) {
|
|
; CHECK-LABEL: test_vextq32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12
|
|
; CHECK-NEXT: ret
|
|
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
|
|
ret <4 x i32> %tmp3
|
|
}
|
|
|
|
; Undef shuffle indices should not prevent matching to VEXT:
|
|
|
|
define <8 x i8> @test_vextd_undef(<8 x i8> %tmp1, <8 x i8> %tmp2) {
|
|
; CHECK-LABEL: test_vextd_undef:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #3
|
|
; CHECK-NEXT: ret
|
|
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
|
|
ret <8 x i8> %tmp3
|
|
}
|
|
|
|
define <8 x i8> @test_vextd_undef2(<8 x i8> %tmp1, <8 x i8> %tmp2) {
|
|
; CHECK-LABEL: test_vextd_undef2:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6
|
|
; CHECK-NEXT: ret
|
|
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
|
|
ret <8 x i8> %tmp3
|
|
}
|
|
|
|
define <16 x i8> @test_vextRq_undef(<16 x i8> %tmp1, <16 x i8> %tmp2) {
|
|
; CHECK-LABEL: test_vextRq_undef:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #7
|
|
; CHECK-NEXT: ret
|
|
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
|
|
ret <16 x i8> %tmp3
|
|
}
|
|
|
|
define <8 x i16> @test_vextRq_undef2(<8 x i16> %tmp1) nounwind {
|
|
; CHECK-LABEL: test_vextRq_undef2:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #10
|
|
; CHECK-NEXT: ret
|
|
%vext = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
|
|
ret <8 x i16> %vext;
|
|
}
|
|
|
|
; Tests for ReconstructShuffle function. Indices have to be carefully
|
|
; chosen to reach lowering phase as a BUILD_VECTOR.
|
|
|
|
; An undef in the shuffle list should still be optimizable
|
|
define <4 x i16> @test_undef(<8 x i16> %tmp1, <8 x i16> %tmp2) {
|
|
; CHECK-SD-LABEL: test_undef:
|
|
; CHECK-SD: // %bb.0:
|
|
; CHECK-SD-NEXT: mov d0, v0.d[1]
|
|
; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v1.4h
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test_undef:
|
|
; CHECK-GI: // %bb.0:
|
|
; CHECK-GI-NEXT: adrp x8, .LCPI10_0
|
|
; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
|
|
; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI10_0]
|
|
; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
|
|
; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
|
|
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-GI-NEXT: ret
|
|
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
|
|
ret <4 x i16> %tmp3
|
|
}
|
|
|
|
define <2 x i64> @test_v2s64(<2 x i64> %a, <2 x i64> %b) {
|
|
; CHECK-LABEL: test_v2s64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
|
|
; CHECK-NEXT: ret
|
|
%s = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 0>
|
|
ret <2 x i64> %s
|
|
}
|
|
|
|
define <2 x ptr> @test_v2p0(<2 x ptr> %a, <2 x ptr> %b) {
|
|
; CHECK-LABEL: test_v2p0:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
|
|
; CHECK-NEXT: ret
|
|
%s = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 3, i32 0>
|
|
ret <2 x ptr> %s
|
|
}
|
|
|
|
define <16 x i8> @reverse_vector_s8x16b(<16 x i8> noundef %x) {
|
|
; CHECK-SD-LABEL: reverse_vector_s8x16b:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: rev64 v0.16b, v0.16b
|
|
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: reverse_vector_s8x16b:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: rev64 v1.16b, v0.16b
|
|
; CHECK-GI-NEXT: mov d0, v1.d[1]
|
|
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-GI-NEXT: ret
|
|
entry:
|
|
%shuffle.i = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
|
|
%shuffle.i6 = shufflevector <16 x i8> %shuffle.i, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
|
%shuffle.i7 = shufflevector <16 x i8> %shuffle.i, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
%shuffle.i5 = shufflevector <8 x i8> %shuffle.i6, <8 x i8> %shuffle.i7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
|
ret <16 x i8> %shuffle.i5
|
|
}
|
|
|
|
define <8 x i16> @reverse_vector_s16x8b(<8 x i16> noundef %x) {
|
|
; CHECK-SD-LABEL: reverse_vector_s16x8b:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: rev64 v0.8h, v0.8h
|
|
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: reverse_vector_s16x8b:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: rev64 v1.8h, v0.8h
|
|
; CHECK-GI-NEXT: mov d0, v1.d[1]
|
|
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-GI-NEXT: ret
|
|
entry:
|
|
%shuffle.i = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
|
|
%shuffle.i6 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
|
%shuffle.i7 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
%shuffle.i5 = shufflevector <4 x i16> %shuffle.i6, <4 x i16> %shuffle.i7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
ret <8 x i16> %shuffle.i5
|
|
}
|
|
|
|
define <4 x i32> @reverse_vector_s32x4b(<4 x i32> noundef %x) {
|
|
; CHECK-SD-LABEL: reverse_vector_s32x4b:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: reverse_vector_s32x4b:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: rev64 v1.4s, v0.4s
|
|
; CHECK-GI-NEXT: mov d0, v1.d[1]
|
|
; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-GI-NEXT: ret
|
|
entry:
|
|
%shuffle.i = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
|
|
%shuffle.i6 = shufflevector <4 x i32> %shuffle.i, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
|
|
%shuffle.i7 = shufflevector <4 x i32> %shuffle.i, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
|
|
%shuffle.i5 = shufflevector <2 x i32> %shuffle.i6, <2 x i32> %shuffle.i7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
ret <4 x i32> %shuffle.i5
|
|
}
|