derek.holloway
7502bf64a4
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193 lines
7.1 KiB
LLVM
193 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define <16 x i8> @div16xi8(<16 x i8> %x) {
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; CHECK-SD-LABEL: div16xi8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: movi v1.16b, #41
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; CHECK-SD-NEXT: smull2 v2.8h, v0.16b, v1.16b
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; CHECK-SD-NEXT: smull v0.8h, v0.8b, v1.8b
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; CHECK-SD-NEXT: uzp2 v0.16b, v0.16b, v2.16b
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; CHECK-SD-NEXT: sshr v0.16b, v0.16b, #2
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; CHECK-SD-NEXT: usra v0.16b, v0.16b, #7
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: div16xi8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v1.16b, #41
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; CHECK-GI-NEXT: smull2 v2.8h, v0.16b, v1.16b
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; CHECK-GI-NEXT: smull v0.8h, v0.8b, v1.8b
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; CHECK-GI-NEXT: uzp2 v1.16b, v0.16b, v2.16b
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; CHECK-GI-NEXT: sshr v0.16b, v1.16b, #2
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; CHECK-GI-NEXT: ushr v0.16b, v0.16b, #7
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; CHECK-GI-NEXT: ssra v0.16b, v1.16b, #2
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; CHECK-GI-NEXT: ret
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%div = sdiv <16 x i8> %x, <i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25>
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ret <16 x i8> %div
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}
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define <8 x i16> @div8xi16(<8 x i16> %x) {
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; CHECK-SD-LABEL: div8xi16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #40815 // =0x9f6f
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; CHECK-SD-NEXT: dup v1.8h, w8
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; CHECK-SD-NEXT: smull2 v2.4s, v0.8h, v1.8h
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; CHECK-SD-NEXT: smull v1.4s, v0.4h, v1.4h
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; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
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; CHECK-SD-NEXT: add v0.8h, v1.8h, v0.8h
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; CHECK-SD-NEXT: sshr v0.8h, v0.8h, #12
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; CHECK-SD-NEXT: usra v0.8h, v0.8h, #15
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: div8xi16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: adrp x8, .LCPI1_0
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; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
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; CHECK-GI-NEXT: smull2 v2.4s, v0.8h, v1.8h
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; CHECK-GI-NEXT: smull v1.4s, v0.4h, v1.4h
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; CHECK-GI-NEXT: uzp2 v1.8h, v1.8h, v2.8h
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; CHECK-GI-NEXT: add v1.8h, v1.8h, v0.8h
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; CHECK-GI-NEXT: sshr v0.8h, v1.8h, #12
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; CHECK-GI-NEXT: ushr v0.8h, v0.8h, #15
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; CHECK-GI-NEXT: ssra v0.8h, v1.8h, #12
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; CHECK-GI-NEXT: ret
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%div = sdiv <8 x i16> %x, <i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577>
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ret <8 x i16> %div
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}
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define <4 x i32> @div32xi4(<4 x i32> %x) {
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; CHECK-SD-LABEL: div32xi4:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #7527 // =0x1d67
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; CHECK-SD-NEXT: movk w8, #28805, lsl #16
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; CHECK-SD-NEXT: dup v1.4s, w8
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; CHECK-SD-NEXT: smull2 v2.2d, v0.4s, v1.4s
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; CHECK-SD-NEXT: smull v0.2d, v0.2s, v1.2s
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; CHECK-SD-NEXT: uzp2 v1.4s, v0.4s, v2.4s
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; CHECK-SD-NEXT: sshr v0.4s, v1.4s, #22
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; CHECK-SD-NEXT: usra v0.4s, v1.4s, #31
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: div32xi4:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: adrp x8, .LCPI2_0
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; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
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; CHECK-GI-NEXT: smull2 v2.2d, v0.4s, v1.4s
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; CHECK-GI-NEXT: smull v0.2d, v0.2s, v1.2s
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; CHECK-GI-NEXT: uzp2 v1.4s, v0.4s, v2.4s
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; CHECK-GI-NEXT: sshr v0.4s, v1.4s, #22
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; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #31
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; CHECK-GI-NEXT: ssra v0.4s, v1.4s, #22
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; CHECK-GI-NEXT: ret
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%div = sdiv <4 x i32> %x, <i32 9542677, i32 9542677, i32 9542677, i32 9542677>
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ret <4 x i32> %div
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}
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define <16 x i8> @udiv16xi8(<16 x i8> %x) {
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; CHECK-LABEL: udiv16xi8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.16b, #121
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; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b
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; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b
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; CHECK-NEXT: uzp2 v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ushr v0.16b, v0.16b, #5
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; CHECK-NEXT: ret
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%div = udiv <16 x i8> %x, <i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68>
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ret <16 x i8> %div
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}
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define <8 x i16> @udiv8xi16(<8 x i16> %x) {
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; CHECK-SD-LABEL: udiv8xi16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #16593 // =0x40d1
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; CHECK-SD-NEXT: dup v1.8h, w8
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; CHECK-SD-NEXT: umull2 v2.4s, v0.8h, v1.8h
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; CHECK-SD-NEXT: umull v1.4s, v0.4h, v1.4h
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; CHECK-SD-NEXT: uzp2 v1.8h, v1.8h, v2.8h
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; CHECK-SD-NEXT: sub v0.8h, v0.8h, v1.8h
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; CHECK-SD-NEXT: usra v1.8h, v0.8h, #1
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; CHECK-SD-NEXT: ushr v0.8h, v1.8h, #12
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: udiv8xi16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: adrp x8, .LCPI4_0
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; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
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; CHECK-GI-NEXT: umull2 v2.4s, v0.8h, v1.8h
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; CHECK-GI-NEXT: umull v1.4s, v0.4h, v1.4h
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; CHECK-GI-NEXT: uzp2 v1.8h, v1.8h, v2.8h
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; CHECK-GI-NEXT: sub v0.8h, v0.8h, v1.8h
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; CHECK-GI-NEXT: usra v1.8h, v0.8h, #1
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; CHECK-GI-NEXT: ushr v0.8h, v1.8h, #12
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; CHECK-GI-NEXT: ret
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%div = udiv <8 x i16> %x, <i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537>
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ret <8 x i16> %div
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}
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define <4 x i32> @udiv32xi4(<4 x i32> %x) {
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; CHECK-SD-LABEL: udiv32xi4:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #16747 // =0x416b
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; CHECK-SD-NEXT: movk w8, #31439, lsl #16
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; CHECK-SD-NEXT: dup v1.4s, w8
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; CHECK-SD-NEXT: umull2 v2.2d, v0.4s, v1.4s
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; CHECK-SD-NEXT: umull v0.2d, v0.2s, v1.2s
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; CHECK-SD-NEXT: uzp2 v0.4s, v0.4s, v2.4s
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; CHECK-SD-NEXT: ushr v0.4s, v0.4s, #22
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: udiv32xi4:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: adrp x8, .LCPI5_0
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; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]
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; CHECK-GI-NEXT: umull2 v2.2d, v0.4s, v1.4s
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; CHECK-GI-NEXT: umull v0.2d, v0.2s, v1.2s
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; CHECK-GI-NEXT: uzp2 v0.4s, v0.4s, v2.4s
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; CHECK-GI-NEXT: ushr v0.4s, v0.4s, #22
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; CHECK-GI-NEXT: ret
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%div = udiv <4 x i32> %x, <i32 8743143, i32 8743143, i32 8743143, i32 8743143>
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ret <4 x i32> %div
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}
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define <2 x i64> @udiv_v2i64(<2 x i64> %a) {
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; CHECK-SD-LABEL: udiv_v2i64:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov x8, #9363 // =0x2493
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; CHECK-SD-NEXT: fmov x10, d0
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; CHECK-SD-NEXT: mov x9, v0.d[1]
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; CHECK-SD-NEXT: movk x8, #37449, lsl #16
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; CHECK-SD-NEXT: movk x8, #18724, lsl #32
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; CHECK-SD-NEXT: movk x8, #9362, lsl #48
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; CHECK-SD-NEXT: umulh x11, x10, x8
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; CHECK-SD-NEXT: umulh x8, x9, x8
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; CHECK-SD-NEXT: sub x10, x10, x11
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; CHECK-SD-NEXT: add x10, x11, x10, lsr #1
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; CHECK-SD-NEXT: sub x9, x9, x8
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; CHECK-SD-NEXT: add x8, x8, x9, lsr #1
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; CHECK-SD-NEXT: lsr x9, x10, #2
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; CHECK-SD-NEXT: fmov d0, x9
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; CHECK-SD-NEXT: lsr x8, x8, #2
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; CHECK-SD-NEXT: mov v0.d[1], x8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: udiv_v2i64:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov x8, #9363 // =0x2493
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; CHECK-GI-NEXT: fmov x10, d0
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; CHECK-GI-NEXT: mov x9, v0.d[1]
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; CHECK-GI-NEXT: movk x8, #37449, lsl #16
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; CHECK-GI-NEXT: movk x8, #18724, lsl #32
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; CHECK-GI-NEXT: movk x8, #9362, lsl #48
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; CHECK-GI-NEXT: umulh x10, x10, x8
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; CHECK-GI-NEXT: umulh x8, x9, x8
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; CHECK-GI-NEXT: fmov d1, x10
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; CHECK-GI-NEXT: mov v1.d[1], x8
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; CHECK-GI-NEXT: sub v0.2d, v0.2d, v1.2d
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; CHECK-GI-NEXT: usra v1.2d, v0.2d, #1
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; CHECK-GI-NEXT: ushr v0.2d, v1.2d, #2
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; CHECK-GI-NEXT: ret
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%r = udiv <2 x i64> %a, splat (i64 7)
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ret <2 x i64> %r
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}
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