derek.holloway
7502bf64a4
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466 lines
18 KiB
LLVM
466 lines
18 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECKLE
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; RUN: llc < %s -mtriple=aarch64_be | FileCheck %s --check-prefixes=CHECKBE
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define <8 x i8> @vtrni8(ptr %A, ptr %B) nounwind {
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; CHECKLE-LABEL: vtrni8:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: ldr d0, [x0]
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; CHECKLE-NEXT: ldr d1, [x1]
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; CHECKLE-NEXT: trn1 v2.8b, v0.8b, v1.8b
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; CHECKLE-NEXT: trn2 v0.8b, v0.8b, v1.8b
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; CHECKLE-NEXT: add v0.8b, v2.8b, v0.8b
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrni8:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ld1 { v0.8b }, [x0]
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; CHECKBE-NEXT: ld1 { v1.8b }, [x1]
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; CHECKBE-NEXT: trn1 v2.8b, v0.8b, v1.8b
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; CHECKBE-NEXT: trn2 v0.8b, v0.8b, v1.8b
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; CHECKBE-NEXT: add v0.8b, v2.8b, v0.8b
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; CHECKBE-NEXT: rev64 v0.8b, v0.8b
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; CHECKBE-NEXT: ret
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%tmp1 = load <8 x i8>, ptr %A
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%tmp2 = load <8 x i8>, ptr %B
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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%tmp5 = add <8 x i8> %tmp3, %tmp4
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ret <8 x i8> %tmp5
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}
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define <4 x i16> @vtrni16(ptr %A, ptr %B) nounwind {
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; CHECKLE-LABEL: vtrni16:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: ldr d0, [x0]
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; CHECKLE-NEXT: ldr d1, [x1]
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; CHECKLE-NEXT: trn1 v2.4h, v0.4h, v1.4h
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; CHECKLE-NEXT: trn2 v0.4h, v0.4h, v1.4h
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; CHECKLE-NEXT: add v0.4h, v2.4h, v0.4h
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrni16:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ld1 { v0.4h }, [x0]
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; CHECKBE-NEXT: ld1 { v1.4h }, [x1]
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; CHECKBE-NEXT: trn1 v2.4h, v0.4h, v1.4h
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; CHECKBE-NEXT: trn2 v0.4h, v0.4h, v1.4h
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; CHECKBE-NEXT: add v0.4h, v2.4h, v0.4h
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; CHECKBE-NEXT: rev64 v0.4h, v0.4h
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; CHECKBE-NEXT: ret
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%tmp1 = load <4 x i16>, ptr %A
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%tmp2 = load <4 x i16>, ptr %B
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = add <4 x i16> %tmp3, %tmp4
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ret <4 x i16> %tmp5
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}
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define <8 x i8> @vtrni16_viabitcast(ptr %A, ptr %B) nounwind {
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; CHECKLE-LABEL: vtrni16_viabitcast:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: ldr d0, [x0]
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; CHECKLE-NEXT: ldr d1, [x1]
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; CHECKLE-NEXT: trn1 v0.4h, v0.4h, v1.4h
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrni16_viabitcast:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ld1 { v0.4h }, [x0]
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; CHECKBE-NEXT: ld1 { v1.4h }, [x1]
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; CHECKBE-NEXT: trn1 v0.4h, v0.4h, v1.4h
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; CHECKBE-NEXT: rev64 v0.4h, v0.4h
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; CHECKBE-NEXT: ret
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%l1 = load <4 x i16>, ptr %A
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%l2 = load <4 x i16>, ptr %B
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%b1 = bitcast <4 x i16> %l1 to <8 x i8>
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%b2 = bitcast <4 x i16> %l2 to <8 x i8>
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%tmp3 = shufflevector <8 x i8> %b1, <8 x i8> %b2, <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 5, i32 12, i32 13>
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ret <8 x i8> %tmp3
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}
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; 2xi32 TRN is redundant with ZIP
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define <2 x i32> @vtrni32(ptr %A, ptr %B) nounwind {
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; CHECKLE-LABEL: vtrni32:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: ldr d0, [x0]
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; CHECKLE-NEXT: ldr d1, [x1]
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; CHECKLE-NEXT: addp v0.2s, v0.2s, v1.2s
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrni32:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ld1 { v0.2s }, [x0]
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; CHECKBE-NEXT: ld1 { v1.2s }, [x1]
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; CHECKBE-NEXT: addp v0.2s, v0.2s, v1.2s
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; CHECKBE-NEXT: rev64 v0.2s, v0.2s
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; CHECKBE-NEXT: ret
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%tmp1 = load <2 x i32>, ptr %A
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%tmp2 = load <2 x i32>, ptr %B
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%tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2>
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%tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3>
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%tmp5 = add <2 x i32> %tmp3, %tmp4
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ret <2 x i32> %tmp5
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}
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define <2 x float> @vtrnf(ptr %A, ptr %B) nounwind {
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; CHECKLE-LABEL: vtrnf:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: ldr d0, [x0]
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; CHECKLE-NEXT: ldr d1, [x1]
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; CHECKLE-NEXT: faddp v0.2s, v0.2s, v1.2s
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrnf:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ld1 { v0.2s }, [x0]
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; CHECKBE-NEXT: ld1 { v1.2s }, [x1]
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; CHECKBE-NEXT: faddp v0.2s, v0.2s, v1.2s
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; CHECKBE-NEXT: rev64 v0.2s, v0.2s
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; CHECKBE-NEXT: ret
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%tmp1 = load <2 x float>, ptr %A
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%tmp2 = load <2 x float>, ptr %B
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%tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2>
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%tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3>
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%tmp5 = fadd <2 x float> %tmp3, %tmp4
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ret <2 x float> %tmp5
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}
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define <16 x i8> @vtrnQi8(ptr %A, ptr %B) nounwind {
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; CHECKLE-LABEL: vtrnQi8:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: ldr q0, [x0]
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; CHECKLE-NEXT: ldr q1, [x1]
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; CHECKLE-NEXT: trn1 v2.16b, v0.16b, v1.16b
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; CHECKLE-NEXT: trn2 v0.16b, v0.16b, v1.16b
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; CHECKLE-NEXT: add v0.16b, v2.16b, v0.16b
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrnQi8:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ld1 { v0.16b }, [x0]
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; CHECKBE-NEXT: ld1 { v1.16b }, [x1]
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; CHECKBE-NEXT: trn1 v2.16b, v0.16b, v1.16b
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; CHECKBE-NEXT: trn2 v0.16b, v0.16b, v1.16b
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; CHECKBE-NEXT: add v0.16b, v2.16b, v0.16b
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; CHECKBE-NEXT: rev64 v0.16b, v0.16b
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; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECKBE-NEXT: ret
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%tmp1 = load <16 x i8>, ptr %A
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%tmp2 = load <16 x i8>, ptr %B
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
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%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31>
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%tmp5 = add <16 x i8> %tmp3, %tmp4
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ret <16 x i8> %tmp5
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}
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define <8 x i16> @vtrnQi16(ptr %A, ptr %B) nounwind {
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; CHECKLE-LABEL: vtrnQi16:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: ldr q0, [x0]
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; CHECKLE-NEXT: ldr q1, [x1]
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; CHECKLE-NEXT: trn1 v2.8h, v0.8h, v1.8h
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; CHECKLE-NEXT: trn2 v0.8h, v0.8h, v1.8h
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; CHECKLE-NEXT: add v0.8h, v2.8h, v0.8h
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrnQi16:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ld1 { v0.8h }, [x0]
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; CHECKBE-NEXT: ld1 { v1.8h }, [x1]
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; CHECKBE-NEXT: trn1 v2.8h, v0.8h, v1.8h
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; CHECKBE-NEXT: trn2 v0.8h, v0.8h, v1.8h
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; CHECKBE-NEXT: add v0.8h, v2.8h, v0.8h
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; CHECKBE-NEXT: rev64 v0.8h, v0.8h
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; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECKBE-NEXT: ret
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%tmp1 = load <8 x i16>, ptr %A
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%tmp2 = load <8 x i16>, ptr %B
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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%tmp5 = add <8 x i16> %tmp3, %tmp4
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ret <8 x i16> %tmp5
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}
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define <4 x i32> @vtrnQi32(ptr %A, ptr %B) nounwind {
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; CHECKLE-LABEL: vtrnQi32:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: ldr q0, [x0]
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; CHECKLE-NEXT: ldr q1, [x1]
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; CHECKLE-NEXT: trn1 v2.4s, v0.4s, v1.4s
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; CHECKLE-NEXT: trn2 v0.4s, v0.4s, v1.4s
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; CHECKLE-NEXT: add v0.4s, v2.4s, v0.4s
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrnQi32:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ld1 { v0.4s }, [x0]
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; CHECKBE-NEXT: ld1 { v1.4s }, [x1]
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; CHECKBE-NEXT: trn1 v2.4s, v0.4s, v1.4s
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; CHECKBE-NEXT: trn2 v0.4s, v0.4s, v1.4s
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; CHECKBE-NEXT: add v0.4s, v2.4s, v0.4s
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; CHECKBE-NEXT: rev64 v0.4s, v0.4s
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; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECKBE-NEXT: ret
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%tmp1 = load <4 x i32>, ptr %A
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%tmp2 = load <4 x i32>, ptr %B
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = add <4 x i32> %tmp3, %tmp4
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ret <4 x i32> %tmp5
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}
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define <4 x float> @vtrnQf(ptr %A, ptr %B) nounwind {
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; CHECKLE-LABEL: vtrnQf:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: ldr q0, [x0]
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; CHECKLE-NEXT: ldr q1, [x1]
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; CHECKLE-NEXT: trn1 v2.4s, v0.4s, v1.4s
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; CHECKLE-NEXT: trn2 v0.4s, v0.4s, v1.4s
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; CHECKLE-NEXT: fadd v0.4s, v2.4s, v0.4s
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrnQf:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: ld1 { v0.4s }, [x0]
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; CHECKBE-NEXT: ld1 { v1.4s }, [x1]
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; CHECKBE-NEXT: trn1 v2.4s, v0.4s, v1.4s
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; CHECKBE-NEXT: trn2 v0.4s, v0.4s, v1.4s
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; CHECKBE-NEXT: fadd v0.4s, v2.4s, v0.4s
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; CHECKBE-NEXT: rev64 v0.4s, v0.4s
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; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECKBE-NEXT: ret
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%tmp1 = load <4 x float>, ptr %A
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%tmp2 = load <4 x float>, ptr %B
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%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
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%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
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%tmp5 = fadd <4 x float> %tmp3, %tmp4
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ret <4 x float> %tmp5
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}
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define <8 x i8> @vtrni8_trn1_flipped(<8 x i8> %A, <8 x i8> %B) nounwind {
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; CHECKLE-LABEL: vtrni8_trn1_flipped:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: trn1 v0.8b, v1.8b, v0.8b
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrni8_trn1_flipped:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: rev64 v0.8b, v0.8b
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; CHECKBE-NEXT: rev64 v1.8b, v1.8b
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; CHECKBE-NEXT: trn1 v0.8b, v1.8b, v0.8b
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; CHECKBE-NEXT: rev64 v0.8b, v0.8b
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; CHECKBE-NEXT: ret
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%tmp1 = shufflevector <8 x i8> %A, <8 x i8> %B, <8 x i32> <i32 8, i32 0, i32 10, i32 2, i32 12, i32 4, i32 14, i32 6>
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ret <8 x i8> %tmp1
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}
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define <8 x i8> @vtrni8_trn2_flipped(<8 x i8> %A, <8 x i8> %B) nounwind {
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; CHECKLE-LABEL: vtrni8_trn2_flipped:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: trn2 v0.8b, v1.8b, v0.8b
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrni8_trn2_flipped:
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; CHECKBE: // %bb.0:
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; CHECKBE-NEXT: rev64 v0.8b, v0.8b
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; CHECKBE-NEXT: rev64 v1.8b, v1.8b
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; CHECKBE-NEXT: trn2 v0.8b, v1.8b, v0.8b
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; CHECKBE-NEXT: rev64 v0.8b, v0.8b
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; CHECKBE-NEXT: ret
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%tmp1 = shufflevector <8 x i8> %A, <8 x i8> %B, <8 x i32> <i32 9, i32 1, i32 11, i32 3, i32 13, i32 5, i32 15, i32 7>
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ret <8 x i8> %tmp1
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}
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define <8 x i8> @vtrni8_both_flipped_with_poison_values(<8 x i8> %A, <8 x i8> %B) nounwind {
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; CHECKLE-LABEL: vtrni8_both_flipped_with_poison_values:
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; CHECKLE: // %bb.0:
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; CHECKLE-NEXT: trn1 v2.8b, v1.8b, v0.8b
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; CHECKLE-NEXT: trn2 v0.8b, v1.8b, v0.8b
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; CHECKLE-NEXT: add v0.8b, v2.8b, v0.8b
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; CHECKLE-NEXT: ret
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;
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; CHECKBE-LABEL: vtrni8_both_flipped_with_poison_values:
|
|
; CHECKBE: // %bb.0:
|
|
; CHECKBE-NEXT: rev64 v0.8b, v0.8b
|
|
; CHECKBE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECKBE-NEXT: trn1 v2.8b, v1.8b, v0.8b
|
|
; CHECKBE-NEXT: trn2 v0.8b, v1.8b, v0.8b
|
|
; CHECKBE-NEXT: add v0.8b, v2.8b, v0.8b
|
|
; CHECKBE-NEXT: rev64 v0.8b, v0.8b
|
|
; CHECKBE-NEXT: ret
|
|
%tmp1 = shufflevector <8 x i8> %A, <8 x i8> %B, <8 x i32> <i32 poison, i32 0, i32 poison, i32 2, i32 poison, i32 4, i32 14, i32 6>
|
|
%tmp2 = shufflevector <8 x i8> %A, <8 x i8> %B, <8 x i32> <i32 poison, i32 1, i32 poison, i32 3, i32 13, i32 5, i32 15, i32 poison>
|
|
%tmp3 = add <8 x i8> %tmp1, %tmp2
|
|
ret <8 x i8> %tmp3
|
|
}
|
|
|
|
; Undef shuffle indices (even at the start of the shuffle mask) should not prevent matching to VTRN:
|
|
|
|
define <8 x i8> @vtrni8_undef(ptr %A, ptr %B) nounwind {
|
|
; CHECKLE-LABEL: vtrni8_undef:
|
|
; CHECKLE: // %bb.0:
|
|
; CHECKLE-NEXT: ldr d0, [x0]
|
|
; CHECKLE-NEXT: ldr d1, [x1]
|
|
; CHECKLE-NEXT: trn1 v2.8b, v0.8b, v1.8b
|
|
; CHECKLE-NEXT: trn2 v0.8b, v0.8b, v1.8b
|
|
; CHECKLE-NEXT: add v0.8b, v2.8b, v0.8b
|
|
; CHECKLE-NEXT: ret
|
|
;
|
|
; CHECKBE-LABEL: vtrni8_undef:
|
|
; CHECKBE: // %bb.0:
|
|
; CHECKBE-NEXT: ld1 { v0.8b }, [x0]
|
|
; CHECKBE-NEXT: ld1 { v1.8b }, [x1]
|
|
; CHECKBE-NEXT: trn1 v2.8b, v0.8b, v1.8b
|
|
; CHECKBE-NEXT: trn2 v0.8b, v0.8b, v1.8b
|
|
; CHECKBE-NEXT: add v0.8b, v2.8b, v0.8b
|
|
; CHECKBE-NEXT: rev64 v0.8b, v0.8b
|
|
; CHECKBE-NEXT: ret
|
|
%tmp1 = load <8 x i8>, ptr %A
|
|
%tmp2 = load <8 x i8>, ptr %B
|
|
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14>
|
|
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15>
|
|
%tmp5 = add <8 x i8> %tmp3, %tmp4
|
|
ret <8 x i8> %tmp5
|
|
}
|
|
|
|
define <8 x i16> @vtrnQi16_undef(ptr %A, ptr %B) nounwind {
|
|
; CHECKLE-LABEL: vtrnQi16_undef:
|
|
; CHECKLE: // %bb.0:
|
|
; CHECKLE-NEXT: ldr q0, [x0]
|
|
; CHECKLE-NEXT: ldr q1, [x1]
|
|
; CHECKLE-NEXT: trn1 v2.8h, v0.8h, v1.8h
|
|
; CHECKLE-NEXT: trn2 v0.8h, v0.8h, v1.8h
|
|
; CHECKLE-NEXT: add v0.8h, v2.8h, v0.8h
|
|
; CHECKLE-NEXT: ret
|
|
;
|
|
; CHECKBE-LABEL: vtrnQi16_undef:
|
|
; CHECKBE: // %bb.0:
|
|
; CHECKBE-NEXT: ld1 { v0.8h }, [x0]
|
|
; CHECKBE-NEXT: ld1 { v1.8h }, [x1]
|
|
; CHECKBE-NEXT: trn1 v2.8h, v0.8h, v1.8h
|
|
; CHECKBE-NEXT: trn2 v0.8h, v0.8h, v1.8h
|
|
; CHECKBE-NEXT: add v0.8h, v2.8h, v0.8h
|
|
; CHECKBE-NEXT: rev64 v0.8h, v0.8h
|
|
; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECKBE-NEXT: ret
|
|
%tmp1 = load <8 x i16>, ptr %A
|
|
%tmp2 = load <8 x i16>, ptr %B
|
|
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14>
|
|
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef>
|
|
%tmp5 = add <8 x i16> %tmp3, %tmp4
|
|
ret <8 x i16> %tmp5
|
|
}
|
|
|
|
define <8 x i16> @vtrnQi16_undef_01(ptr %A, ptr %B) nounwind {
|
|
; CHECKLE-LABEL: vtrnQi16_undef_01:
|
|
; CHECKLE: // %bb.0:
|
|
; CHECKLE-NEXT: ldr q0, [x0]
|
|
; CHECKLE-NEXT: ldr q1, [x1]
|
|
; CHECKLE-NEXT: trn1 v2.8h, v0.8h, v1.8h
|
|
; CHECKLE-NEXT: trn2 v0.8h, v0.8h, v1.8h
|
|
; CHECKLE-NEXT: add v0.8h, v2.8h, v0.8h
|
|
; CHECKLE-NEXT: ret
|
|
;
|
|
; CHECKBE-LABEL: vtrnQi16_undef_01:
|
|
; CHECKBE: // %bb.0:
|
|
; CHECKBE-NEXT: ld1 { v0.8h }, [x0]
|
|
; CHECKBE-NEXT: ld1 { v1.8h }, [x1]
|
|
; CHECKBE-NEXT: trn1 v2.8h, v0.8h, v1.8h
|
|
; CHECKBE-NEXT: trn2 v0.8h, v0.8h, v1.8h
|
|
; CHECKBE-NEXT: add v0.8h, v2.8h, v0.8h
|
|
; CHECKBE-NEXT: rev64 v0.8h, v0.8h
|
|
; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECKBE-NEXT: ret
|
|
%tmp1 = load <8 x i16>, ptr %A
|
|
%tmp2 = load <8 x i16>, ptr %B
|
|
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 poison, i32 poison, i32 2, i32 poison, i32 4, i32 12, i32 6, i32 14>
|
|
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 poison, i32 poison, i32 3, i32 11, i32 poison, i32 13, i32 poison, i32 poison>
|
|
%tmp5 = add <8 x i16> %tmp3, %tmp4
|
|
ret <8 x i16> %tmp5
|
|
}
|
|
|
|
define <8 x i16> @vtrnQi16_undef_0(ptr %A, ptr %B) nounwind {
|
|
; CHECKLE-LABEL: vtrnQi16_undef_0:
|
|
; CHECKLE: // %bb.0:
|
|
; CHECKLE-NEXT: ldr q0, [x0]
|
|
; CHECKLE-NEXT: ldr q1, [x1]
|
|
; CHECKLE-NEXT: trn1 v2.8h, v0.8h, v1.8h
|
|
; CHECKLE-NEXT: trn2 v0.8h, v0.8h, v1.8h
|
|
; CHECKLE-NEXT: add v0.8h, v2.8h, v0.8h
|
|
; CHECKLE-NEXT: ret
|
|
;
|
|
; CHECKBE-LABEL: vtrnQi16_undef_0:
|
|
; CHECKBE: // %bb.0:
|
|
; CHECKBE-NEXT: ld1 { v0.8h }, [x0]
|
|
; CHECKBE-NEXT: ld1 { v1.8h }, [x1]
|
|
; CHECKBE-NEXT: trn1 v2.8h, v0.8h, v1.8h
|
|
; CHECKBE-NEXT: trn2 v0.8h, v0.8h, v1.8h
|
|
; CHECKBE-NEXT: add v0.8h, v2.8h, v0.8h
|
|
; CHECKBE-NEXT: rev64 v0.8h, v0.8h
|
|
; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECKBE-NEXT: ret
|
|
%tmp1 = load <8 x i16>, ptr %A
|
|
%tmp2 = load <8 x i16>, ptr %B
|
|
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 poison, i32 8, i32 poison, i32 poison, i32 4, i32 12, i32 6, i32 14>
|
|
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 poison, i32 9, i32 3, i32 11, i32 5, i32 13, i32 poison, i32 poison>
|
|
%tmp5 = add <8 x i16> %tmp3, %tmp4
|
|
ret <8 x i16> %tmp5
|
|
}
|
|
|
|
define <4 x i32> @vtrnQi32_undef_1(ptr %A, ptr %B) nounwind {
|
|
; CHECKLE-LABEL: vtrnQi32_undef_1:
|
|
; CHECKLE: // %bb.0:
|
|
; CHECKLE-NEXT: ldr q0, [x0]
|
|
; CHECKLE-NEXT: ldr q1, [x1]
|
|
; CHECKLE-NEXT: trn1 v2.4s, v0.4s, v1.4s
|
|
; CHECKLE-NEXT: trn2 v0.4s, v0.4s, v1.4s
|
|
; CHECKLE-NEXT: add v0.4s, v2.4s, v0.4s
|
|
; CHECKLE-NEXT: ret
|
|
;
|
|
; CHECKBE-LABEL: vtrnQi32_undef_1:
|
|
; CHECKBE: // %bb.0:
|
|
; CHECKBE-NEXT: ld1 { v0.4s }, [x0]
|
|
; CHECKBE-NEXT: ld1 { v1.4s }, [x1]
|
|
; CHECKBE-NEXT: trn1 v2.4s, v0.4s, v1.4s
|
|
; CHECKBE-NEXT: trn2 v0.4s, v0.4s, v1.4s
|
|
; CHECKBE-NEXT: add v0.4s, v2.4s, v0.4s
|
|
; CHECKBE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECKBE-NEXT: ret
|
|
%tmp1 = load <4 x i32>, ptr %A
|
|
%tmp2 = load <4 x i32>, ptr %B
|
|
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 poison, i32 2, i32 6>
|
|
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 poison, i32 3, i32 7>
|
|
%tmp5 = add <4 x i32> %tmp3, %tmp4
|
|
ret <4 x i32> %tmp5
|
|
}
|
|
|
|
define <16 x i8> @vtrnQi8_undef_012(ptr %A, ptr %B) nounwind {
|
|
; CHECKLE-LABEL: vtrnQi8_undef_012:
|
|
; CHECKLE: // %bb.0:
|
|
; CHECKLE-NEXT: ldr q0, [x0]
|
|
; CHECKLE-NEXT: ldr q1, [x1]
|
|
; CHECKLE-NEXT: trn1 v2.16b, v0.16b, v1.16b
|
|
; CHECKLE-NEXT: trn2 v0.16b, v0.16b, v1.16b
|
|
; CHECKLE-NEXT: add v0.16b, v2.16b, v0.16b
|
|
; CHECKLE-NEXT: ret
|
|
;
|
|
; CHECKBE-LABEL: vtrnQi8_undef_012:
|
|
; CHECKBE: // %bb.0:
|
|
; CHECKBE-NEXT: ld1 { v0.16b }, [x0]
|
|
; CHECKBE-NEXT: ld1 { v1.16b }, [x1]
|
|
; CHECKBE-NEXT: trn1 v2.16b, v0.16b, v1.16b
|
|
; CHECKBE-NEXT: trn2 v0.16b, v0.16b, v1.16b
|
|
; CHECKBE-NEXT: add v0.16b, v2.16b, v0.16b
|
|
; CHECKBE-NEXT: rev64 v0.16b, v0.16b
|
|
; CHECKBE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECKBE-NEXT: ret
|
|
%tmp1 = load <16 x i8>, ptr %A
|
|
%tmp2 = load <16 x i8>, ptr %B
|
|
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 18, i32 4, i32 poison, i32 6, i32 22, i32 poison, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
|
|
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 poison, i32 poison, i32 poison, i32 19, i32 5, i32 21, i32 7, i32 poison, i32 9, i32 25, i32 11, i32 27, i32 poison, i32 29, i32 15, i32 31>
|
|
%tmp5 = add <16 x i8> %tmp3, %tmp4
|
|
ret <16 x i8> %tmp5
|
|
}
|