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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=arm64-linux-gnuabi < %s | FileCheck %s
; The following tests is to check the correctness of reversing input operand
; of vext by enumerating all cases of using two undefs in shuffle masks.
define <4 x i16> @vext_6701_0(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_6701_0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_12(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_6701_12:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: dup v0.2s, v0.s[0]
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_13(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_6701_13:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 undef, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_14(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_6701_14:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 0, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_23(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_6701_23:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 undef, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_24(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_6701_24:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #4
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 0, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_34(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_6701_34:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: dup v0.2s, v1.s[1]
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 undef, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_0(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_5670_0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_12(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_5670_12:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 7, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_13(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_5670_13:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 undef, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_14(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_5670_14:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 7, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_23(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_5670_23:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 undef, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_24(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_5670_24:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rev32 v0.4h, v1.4h
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 7, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_34(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_5670_34:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #2
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 undef, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_0(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_7012_0:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_12(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_7012_12:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 1, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_13(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_7012_13:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: rev32 v0.4h, v0.4h
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 undef, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_14(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_7012_14:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_23(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_7012_23:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 undef, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_24(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_7012_24:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 1, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_34(<4 x i16> %a1, <4 x i16> %a2) {
; CHECK-LABEL: vext_7012_34:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #6
; CHECK-NEXT: ret
entry:
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 undef, i32 undef>
ret <4 x i16> %x
}
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