derek.holloway
7502bf64a4
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168 lines
6.9 KiB
LLVM
168 lines
6.9 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-FPR64-NOZCZ-FPR128
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64,+fullfp16 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-FPR64-NOZCZ-FPR128-FULLFP16
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; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+fullfp16 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64,+zcz-fpr128 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-FPR64-ZCZ-FPR128
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; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s --match-full-lines -check-prefixes=ALL,FP-WORKAROUND
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; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s --match-full-lines -check-prefixes=ALL,NOZCZ-FPR64-ZCZ-FPR128
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s --match-full-lines -check-prefixes=ALL,ZCZ-FPR64
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define half @tf16() {
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entry:
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; ALL-LABEL: {{_?}}tf16:{{ *}}{{(;|//)}}{{ *}}@tf16
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; FP-WORKAROUND: fmov s0, wzr
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; NOZCZ-FPR64-NOZCZ-FPR128: fmov s0, wzr
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; NOZCZ-FPR64-NOZCZ-FPR128-FULLFP16: fmov h0, wzr
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; ZCZ-FPR64: movi d0, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret half 0.0
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}
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define float @tf32() {
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entry:
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; ALL-LABEL: {{_?}}tf32:{{ *}}{{(;|//)}}{{ *}}@tf32
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; FP-WORKAROUND: fmov s0, wzr
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; NOZCZ-FPR64-NOZCZ-FPR128: fmov s0, wzr
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; ZCZ-FPR64: movi d0, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret float 0.0
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}
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define double @td64() {
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entry:
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; ALL-LABEL: {{_?}}td64:{{ *}}{{(;|//)}}{{ *}}@td64
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; FP-WORKAROUND: fmov d0, xzr
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; NOZCZ-FPR64-NOZCZ-FPR128: fmov d0, xzr
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; ZCZ-FPR64: movi d0, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret double 0.0
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}
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define <8 x i8> @tv8i8() {
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entry:
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; ALL-LABEL: {{_?}}tv8i8:{{ *}}{{(;|//)}}{{ *}}@tv8i8
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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}
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define <4 x i16> @tv4i16() {
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entry:
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; ALL-LABEL: {{_?}}tv4i16:{{ *}}{{(;|//)}}{{ *}}@tv4i16
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <4 x i16> <i16 0, i16 0, i16 0, i16 0>
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}
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define <2 x i32> @tv2i32() {
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entry:
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; ALL-LABEL: {{_?}}tv2i32:{{ *}}{{(;|//)}}{{ *}}@tv2i32
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <2 x i32> <i32 0, i32 0>
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}
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define <2 x float> @tv2f32() {
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entry:
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; ALL-LABEL: {{_?}}tv2f32:{{ *}}{{(;|//)}}{{ *}}@tv2f32
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <2 x float> <float 0.0, float 0.0>
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}
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define <16 x i8> @tv16i8() {
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entry:
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; ALL-LABEL: {{_?}}tv16i8:{{ *}}{{(;|//)}}{{ *}}@tv16i8
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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}
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define <8 x i16> @tv8i16() {
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entry:
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; ALL-LABEL: {{_?}}tv8i16:{{ *}}{{(;|//)}}{{ *}}@tv8i16
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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}
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define <4 x i32> @tv4i32() {
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entry:
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; ALL-LABEL: {{_?}}tv4i32:{{ *}}{{(;|//)}}{{ *}}@tv4i32
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <4 x i32> <i32 0, i32 0, i32 0, i32 0>
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}
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define <2 x i64> @tv2i64() {
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entry:
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; ALL-LABEL: {{_?}}tv2i64:{{ *}}{{(;|//)}}{{ *}}@tv2i64
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <2 x i64> <i64 0, i64 0>
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}
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define <4 x float> @tv4f32() {
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entry:
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; ALL-LABEL: {{_?}}tv4f32:{{ *}}{{(;|//)}}{{ *}}@tv4f32
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
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}
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define <2 x double> @tv2d64() {
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entry:
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; ALL-LABEL: {{_?}}tv2d64:{{ *}}{{(;|//)}}{{ *}}@tv2d64
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; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0
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; NOZCZ-FPR64-NOZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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; NOZCZ-FPR64-ZCZ-FPR128: movi{{(.2d)?}} v0{{(.2d)?}}, #0000000000000000
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ret <2 x double> <double 0.0, double 0.0>
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}
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; We used to produce spills+reloads for a Q register with zero cycle zeroing
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; enabled.
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; ALL-LABEL: {{_?}}foo:{{ *}}{{(;|//)}}{{ *}}@foo
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; ALL-NOT: str q{{[0-9]+}}
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; ALL-NOT: ldr q{{[0-9]+}}
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define double @foo(i32 %n) {
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entry:
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br label %for.body
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for.body:
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%phi0 = phi double [ 1.0, %entry ], [ %v0, %for.body ]
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%i.076 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%conv21 = sitofp i32 %i.076 to double
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%call = tail call fast double @sin(double %conv21)
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%cmp.i = fcmp fast olt double %phi0, %call
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%v0 = select i1 %cmp.i, double %call, double %phi0
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%inc = add nuw nsw i32 %i.076, 1
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%cmp = icmp slt i32 %inc, %n
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret double %v0
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}
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declare double @sin(double)
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