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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/bool-ext-inc.ll
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derek.holloway 7502bf64a4
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

106 lines
3.1 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <4 x i32> @sextbool_add_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
; CHECK-LABEL: sextbool_add_vector:
; CHECK: // %bb.0:
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-NEXT: add v0.4s, v2.4s, v0.4s
; CHECK-NEXT: ret
%c = icmp eq <4 x i32> %c1, %c2
%b = sext <4 x i1> %c to <4 x i32>
%s = add <4 x i32> %x, %b
ret <4 x i32> %s
}
define <4 x i32> @zextbool_sub_vector(<4 x i32> %c1, <4 x i32> %c2, <4 x i32> %x) {
; CHECK-SD-LABEL: zextbool_sub_vector:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-SD-NEXT: add v0.4s, v2.4s, v0.4s
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: zextbool_sub_vector:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: movi v3.4s, #1
; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b
; CHECK-GI-NEXT: sub v0.4s, v2.4s, v0.4s
; CHECK-GI-NEXT: ret
%c = icmp eq <4 x i32> %c1, %c2
%b = zext <4 x i1> %c to <4 x i32>
%s = sub <4 x i32> %x, %b
ret <4 x i32> %s
}
define i32 @assertsext_sub_1(i1 signext %cond, i32 %y) {
; CHECK-SD-LABEL: assertsext_sub_1:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: add w0, w1, w0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: assertsext_sub_1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and w8, w0, #0x1
; CHECK-GI-NEXT: sub w0, w1, w8
; CHECK-GI-NEXT: ret
%e = zext i1 %cond to i32
%r = sub i32 %y, %e
ret i32 %r
}
define i32 @assertsext_add_1(i1 signext %cond, i32 %y) {
; CHECK-SD-LABEL: assertsext_add_1:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sub w0, w1, w0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: assertsext_add_1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and w8, w0, #0x1
; CHECK-GI-NEXT: add w0, w8, w1
; CHECK-GI-NEXT: ret
%e = zext i1 %cond to i32
%r = add i32 %e, %y
ret i32 %r
}
define i32 @assertsext_add_1_commute(i1 signext %cond, i32 %y) {
; CHECK-SD-LABEL: assertsext_add_1_commute:
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sub w0, w1, w0
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: assertsext_add_1_commute:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and w8, w0, #0x1
; CHECK-GI-NEXT: add w0, w1, w8
; CHECK-GI-NEXT: ret
%e = zext i1 %cond to i32
%r = add i32 %y, %e
ret i32 %r
}
define i32 @callee_signext_i1(i1 signext %0) {
; CHECK-LABEL: callee_signext_i1:
; CHECK: // %bb.0:
; CHECK-NEXT: ret
%r = sext i1 %0 to i32
ret i32 %r
}
define i32 @caller_signext_i1() {
; CHECK-LABEL: caller_signext_i1:
; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w0, #-1 // =0xffffffff
; CHECK-NEXT: bl callee_signext_i1
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret
%r = call i32 @callee_signext_i1(i1 signext true)
ret i32 %r
}