derek.holloway
7502bf64a4
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92 lines
2.9 KiB
LLVM
92 lines
2.9 KiB
LLVM
; RUN: llc -mtriple aarch64 -mattr=+bti < %s | FileCheck %s
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; RUN: llc -mtriple aarch64 -global-isel -mattr=+bti < %s | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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; When BTI is enabled, all indirect tail-calls must use x16 or x17 (the intra
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; procedure call scratch registers) to hold the address, as these instructions
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; are allowed to target the "BTI c" instruction at the start of the target
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; function. The alternative to this would be to start functions with "BTI jc",
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; which increases the number of potential ways they could be called, and
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; weakens the security protections.
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define void @bti_disabled(ptr %p) {
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entry:
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tail call void %p()
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; CHECK: br x0
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ret void
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}
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define void @bti_enabled(ptr %p) "branch-target-enforcement" {
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entry:
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tail call void %p()
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; CHECK: br {{x16|x17}}
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ret void
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}
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define void @bti_enabled_force_x10(ptr %p) "branch-target-enforcement" {
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entry:
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%p_x10 = tail call ptr asm "", "={x10},{x10},~{lr}"(ptr %p)
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tail call void %p_x10()
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; CHECK: br {{x16|x17}}
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ret void
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}
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; sign-return-address places no further restrictions on the tail-call register.
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define void @bti_enabled_pac_enabled(ptr %p) "branch-target-enforcement" "sign-return-address"="all" {
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entry:
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tail call void %p()
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; CHECK: br {{x16|x17}}
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ret void
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}
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define void @bti_enabled_pac_enabled_force_x10(ptr %p) "branch-target-enforcement" "sign-return-address"="all" {
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entry:
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%p_x10 = tail call ptr asm "", "={x10},{x10},~{lr}"(ptr %p)
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tail call void %p_x10()
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; CHECK: br {{x16|x17}}
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ret void
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}
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; PAuthLR needs to use x16 to hold the address of the signing instruction. That
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; can't be changed because the hint instruction only uses that register, so the
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; only choice for the tail-call function pointer is x17.
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define void @bti_enabled_pac_pc_enabled(ptr %p) "branch-target-enforcement" "sign-return-address"="all" "branch-protection-pauth-lr" {
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entry:
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tail call void %p()
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; CHECK: br x17
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ret void
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}
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define void @bti_enabled_pac_pc_enabled_force_x16(ptr %p) "branch-target-enforcement" "sign-return-address"="all" "branch-protection-pauth-lr" {
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entry:
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%p_x16 = tail call ptr asm "", "={x16},{x16},~{lr}"(ptr %p)
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tail call void %p_x16()
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; CHECK: br x17
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ret void
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}
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; PAuthLR by itself prevents x16 from being used, but any other
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; non-callee-saved register can be used.
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define void @pac_pc_enabled(ptr %p) "sign-return-address"="all" "branch-protection-pauth-lr" {
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entry:
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tail call void %p()
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; CHECK: br {{(x[0-9]|x1[0-578])$}}
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ret void
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}
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define void @pac_pc_enabled_force_x16(ptr %p) "sign-return-address"="all" "branch-protection-pauth-lr" {
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entry:
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%p_x16 = tail call ptr asm "", "={x16},{x16},~{lr}"(ptr %p)
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tail call void %p_x16()
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; CHECK: br {{(x[0-9]|x1[0-578])$}}
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ret void
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}
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define void @pac_pc_enabled_force_x17(ptr %p) "sign-return-address"="all" "branch-protection-pauth-lr" {
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entry:
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%p_x17 = tail call ptr asm "", "={x17},{x17},~{lr}"(ptr %p)
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tail call void %p_x17()
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; CHECK: br x17
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ret void
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}
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