derek.holloway
7502bf64a4
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186 lines
4.4 KiB
LLVM
186 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-gnu-linux -o - | FileCheck %s
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; These tests make sure that the `cmp` instruction is rendered with an
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; instruction that checks the sign bit of the original unextended data
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; (%in) instead of the sign bit of the sign extended one that is
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; created by the type legalization process.
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;
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; The tests are subdivided in tests that determine the sign bit
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; looking through a `sign_extend_inreg` and tests that determine the
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; sign bit looking through a `sign_extend`.
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define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: f_i8_sign_extend_inreg:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sxtb w8, w0
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; CHECK-NEXT: cmn w8, #1
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; CHECK-NEXT: csel w8, w1, w2, gt
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; CHECK-NEXT: add w0, w8, w0, uxtb
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp sgt i8 %in, -1
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%ext = zext i8 %in to i32
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br i1 %cmp, label %A, label %B
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A:
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%retA = add i32 %ext, %a
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ret i32 %retA
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B:
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%retB = add i32 %ext, %b
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ret i32 %retB
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}
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define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: f_i16_sign_extend_inreg:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sxth w8, w0
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; CHECK-NEXT: cmn w8, #1
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; CHECK-NEXT: csel w8, w1, w2, gt
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; CHECK-NEXT: add w0, w8, w0, uxth
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp sgt i16 %in, -1
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%ext = zext i16 %in to i32
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br i1 %cmp, label %A, label %B
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A:
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%retA = add i32 %ext, %a
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ret i32 %retA
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B:
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%retB = add i32 %ext, %b
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ret i32 %retB
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}
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define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: f_i32_sign_extend_inreg:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmn w0, #1
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; CHECK-NEXT: csel x8, x1, x2, gt
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; CHECK-NEXT: add x0, x8, w0, uxtw
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp sgt i32 %in, -1
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%ext = zext i32 %in to i64
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br i1 %cmp, label %A, label %B
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A:
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%retA = add i64 %ext, %a
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ret i64 %retA
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B:
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%retB = add i64 %ext, %b
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ret i64 %retB
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}
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define i32 @g_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: g_i8_sign_extend_inreg:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: tst w0, #0x80
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; CHECK-NEXT: csel w8, w1, w2, ne
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; CHECK-NEXT: add w0, w8, w0, uxtb
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i8 %in, 0
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%ext = zext i8 %in to i32
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br i1 %cmp, label %A, label %B
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A:
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%retA = add i32 %ext, %a
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ret i32 %retA
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B:
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%retB = add i32 %ext, %b
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ret i32 %retB
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}
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define i32 @g_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: g_i16_sign_extend_inreg:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: tst w0, #0x8000
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; CHECK-NEXT: csel w8, w1, w2, ne
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; CHECK-NEXT: add w0, w8, w0, uxth
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i16 %in, 0
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%ext = zext i16 %in to i32
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br i1 %cmp, label %A, label %B
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A:
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%retA = add i32 %ext, %a
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ret i32 %retA
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B:
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%retB = add i32 %ext, %b
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ret i32 %retB
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}
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define i64 @g_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: g_i32_sign_extend_inreg:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: csel x8, x1, x2, mi
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; CHECK-NEXT: add x0, x8, w0, uxtw
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i32 %in, 0
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%ext = zext i32 %in to i64
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br i1 %cmp, label %A, label %B
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A:
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%retA = add i64 %ext, %a
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ret i64 %retA
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B:
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%retB = add i64 %ext, %b
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ret i64 %retB
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}
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define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: f_i32_sign_extend_i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sxtw x8, w0
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; CHECK-NEXT: cmn x8, #1
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; CHECK-NEXT: csel x8, x1, x2, gt
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; CHECK-NEXT: add x0, x8, w0, uxtw
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; CHECK-NEXT: ret
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entry:
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%inext = sext i32 %in to i64
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%cmp = icmp sgt i64 %inext, -1
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%ext = zext i32 %in to i64
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br i1 %cmp, label %A, label %B
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A:
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%retA = add i64 %ext, %a
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ret i64 %retA
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B:
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%retB = add i64 %ext, %b
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ret i64 %retB
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}
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define i64 @g_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: g_i32_sign_extend_i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: tst w0, #0x80000000
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; CHECK-NEXT: csel x8, x1, x2, ne
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; CHECK-NEXT: add x0, x8, w0, uxtw
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; CHECK-NEXT: ret
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entry:
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%inext = sext i32 %in to i64
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%cmp = icmp slt i64 %inext, 0
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%ext = zext i32 %in to i64
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br i1 %cmp, label %A, label %B
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A:
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%retA = add i64 %ext, %a
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ret i64 %retA
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B:
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%retB = add i64 %ext, %b
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ret i64 %retB
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}
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