derek.holloway
7502bf64a4
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157 lines
5.7 KiB
YAML
157 lines
5.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -o - -aarch64-cb-offset-bits=3 \
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# RUN: -run-pass=branch-relaxation -verify-machineinstrs -simplify-mir %s | \
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# RUN: FileCheck -check-prefix=RELAX %s
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# RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -o - -aarch64-cb-offset-bits=9 \
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# RUN: -run-pass=branch-relaxation -verify-machineinstrs -simplify-mir %s | \
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# RUN: FileCheck -check-prefix=NO-RELAX %s
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---
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name: relax_cb
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr32 }
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liveins:
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- { reg: '$w0', virtual-reg: '%0' }
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- { reg: '$w1', virtual-reg: '%1' }
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body: |
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; RELAX-LABEL: name: relax_cb
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; RELAX: bb.0:
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; RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; RELAX-NEXT: CBWPrr 1, [[COPY]], [[COPY1]], %bb.1
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; RELAX-NEXT: B %bb.2
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; RELAX-NEXT: {{ $}}
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; RELAX-NEXT: bb.1:
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; RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
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; RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
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; RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
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; RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
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; RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
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; RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
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; RELAX-NEXT: {{ $}}
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; RELAX-NEXT: bb.2:
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; RELAX-NEXT: RET_ReallyLR implicit $w0
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;
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; NO-RELAX-LABEL: name: relax_cb
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; NO-RELAX: bb.0:
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; NO-RELAX-NEXT: successors: %bb.1, %bb.2
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; NO-RELAX-NEXT: {{ $}}
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; NO-RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; NO-RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; NO-RELAX-NEXT: CBWPrr 0, [[COPY]], [[COPY1]], %bb.2
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; NO-RELAX-NEXT: {{ $}}
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; NO-RELAX-NEXT: bb.1:
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; NO-RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
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; NO-RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
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; NO-RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
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; NO-RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
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; NO-RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
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; NO-RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
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; NO-RELAX-NEXT: {{ $}}
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; NO-RELAX-NEXT: bb.2:
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; NO-RELAX-NEXT: RET_ReallyLR implicit $w0
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bb.0:
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successors: %bb.1, %bb.2
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%0:gpr32 = COPY $w0
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%1:gpr32 = COPY $w1
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CBWPrr 0, %0, %1, %bb.2
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bb.1:
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successors: %bb.2
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%2:gpr32 = ADDWrr %0, %1
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%3:gpr32 = ADDWrr %2, %1
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%4:gpr32 = ADDWrr %3, %2
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%5:gpr32 = ADDWrr %4, %3
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%6:gpr32 = ADDWrr %5, %4
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$w0 = ADDWrr %6, %5
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bb.2:
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RET_ReallyLR implicit $w0
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...
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---
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name: relax_and_split_block
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr32 }
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- { id: 1, class: gpr32 }
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liveins:
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- { reg: '$w0', virtual-reg: '%0' }
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- { reg: '$w1', virtual-reg: '%1' }
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body: |
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; RELAX-LABEL: name: relax_and_split_block
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; RELAX: bb.0:
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; RELAX-NEXT: liveins: $w0, $w1
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; RELAX-NEXT: {{ $}}
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; RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; RELAX-NEXT: CBWPrr 1, [[COPY]], [[COPY1]], %bb.3
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; RELAX-NEXT: B %bb.2
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; RELAX-NEXT: {{ $}}
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; RELAX-NEXT: bb.3:
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; RELAX-NEXT: liveins: $w0, $w1
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; RELAX-NEXT: {{ $}}
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; RELAX-NEXT: CBWPrr 0, [[COPY]], [[COPY1]], %bb.1
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; RELAX-NEXT: B %bb.2
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; RELAX-NEXT: {{ $}}
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; RELAX-NEXT: bb.1:
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; RELAX-NEXT: liveins: $w0, $w1
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; RELAX-NEXT: {{ $}}
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; RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
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; RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
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; RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
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; RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
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; RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
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; RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
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; RELAX-NEXT: {{ $}}
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; RELAX-NEXT: bb.2:
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; RELAX-NEXT: liveins: $w0, $w1
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; RELAX-NEXT: {{ $}}
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; RELAX-NEXT: RET_ReallyLR implicit $w0
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;
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; NO-RELAX-LABEL: name: relax_and_split_block
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; NO-RELAX: bb.0:
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; NO-RELAX-NEXT: successors: %bb.1, %bb.2
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; NO-RELAX-NEXT: liveins: $w0, $w1
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; NO-RELAX-NEXT: {{ $}}
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; NO-RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; NO-RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; NO-RELAX-NEXT: CBWPrr 0, [[COPY]], [[COPY1]], %bb.2
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; NO-RELAX-NEXT: CBWPrr 1, [[COPY]], [[COPY1]], %bb.2
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; NO-RELAX-NEXT: {{ $}}
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; NO-RELAX-NEXT: bb.1:
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; NO-RELAX-NEXT: liveins: $w0, $w1
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; NO-RELAX-NEXT: {{ $}}
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; NO-RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
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; NO-RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
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; NO-RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
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; NO-RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
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; NO-RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
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; NO-RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
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; NO-RELAX-NEXT: {{ $}}
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; NO-RELAX-NEXT: bb.2:
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; NO-RELAX-NEXT: liveins: $w0, $w1
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; NO-RELAX-NEXT: {{ $}}
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; NO-RELAX-NEXT: RET_ReallyLR implicit $w0
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $w0, $w1
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%0:gpr32 = COPY $w0
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%1:gpr32 = COPY $w1
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CBWPrr 0, %0, %1, %bb.2
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CBWPrr 1, %0, %1, %bb.2
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bb.1:
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successors: %bb.2
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liveins: $w0, $w1
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%2:gpr32 = ADDWrr %0, %1
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%3:gpr32 = ADDWrr %2, %1
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%4:gpr32 = ADDWrr %3, %2
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%5:gpr32 = ADDWrr %4, %3
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%6:gpr32 = ADDWrr %5, %4
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$w0 = ADDWrr %6, %5
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bb.2:
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liveins: $w0, $w1
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RET_ReallyLR implicit $w0
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...
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