derek.holloway
7502bf64a4
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109 lines
5.6 KiB
LLVM
109 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s
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target triple = "aarch64"
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; Expected to transform
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define <vscale x 4 x i32> @complex_mul_v4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: complex_mul_v4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: cmla z2.s, z1.s, z0.s, #0
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; CHECK-NEXT: cmla z2.s, z1.s, z0.s, #90
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; CHECK-NEXT: mov z0.d, z2.d
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; CHECK-NEXT: ret
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entry:
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%a.deinterleaved = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %a)
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%a.real = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %a.deinterleaved, 0
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%a.imag = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %a.deinterleaved, 1
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%b.deinterleaved = tail call { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32> %b)
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%b.real = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %b.deinterleaved, 0
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%b.imag = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } %b.deinterleaved, 1
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%0 = mul <vscale x 2 x i32> %b.imag, %a.real
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%1 = mul <vscale x 2 x i32> %b.real, %a.imag
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%2 = add <vscale x 2 x i32> %1, %0
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%3 = mul <vscale x 2 x i32> %b.real, %a.real
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%4 = mul <vscale x 2 x i32> %a.imag, %b.imag
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%5 = sub <vscale x 2 x i32> %3, %4
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%interleaved.vec = tail call <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32> %5, <vscale x 2 x i32> %2)
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ret <vscale x 4 x i32> %interleaved.vec
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}
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; Expected to transform
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define <vscale x 8 x i32> @complex_mul_v8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
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; CHECK-LABEL: complex_mul_v8i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v4.2d, #0000000000000000
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; CHECK-NEXT: movi v5.2d, #0000000000000000
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; CHECK-NEXT: cmla z5.s, z2.s, z0.s, #0
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; CHECK-NEXT: cmla z4.s, z3.s, z1.s, #0
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; CHECK-NEXT: cmla z5.s, z2.s, z0.s, #90
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; CHECK-NEXT: cmla z4.s, z3.s, z1.s, #90
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: mov z1.d, z4.d
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; CHECK-NEXT: ret
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entry:
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%a.deinterleaved = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %a)
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%a.real = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %a.deinterleaved, 0
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%a.imag = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %a.deinterleaved, 1
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%b.deinterleaved = tail call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32> %b)
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%b.real = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %b.deinterleaved, 0
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%b.imag = extractvalue { <vscale x 4 x i32>, <vscale x 4 x i32> } %b.deinterleaved, 1
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%0 = mul <vscale x 4 x i32> %b.imag, %a.real
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%1 = mul <vscale x 4 x i32> %b.real, %a.imag
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%2 = add <vscale x 4 x i32> %1, %0
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%3 = mul <vscale x 4 x i32> %b.real, %a.real
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%4 = mul <vscale x 4 x i32> %a.imag, %b.imag
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%5 = sub <vscale x 4 x i32> %3, %4
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%interleaved.vec = tail call <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32> %5, <vscale x 4 x i32> %2)
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ret <vscale x 8 x i32> %interleaved.vec
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}
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; Expected to transform
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define <vscale x 16 x i32> @complex_mul_v16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {
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; CHECK-LABEL: complex_mul_v16i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v24.2d, #0000000000000000
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; CHECK-NEXT: movi v25.2d, #0000000000000000
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; CHECK-NEXT: movi v26.2d, #0000000000000000
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; CHECK-NEXT: movi v27.2d, #0000000000000000
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; CHECK-NEXT: cmla z24.s, z4.s, z0.s, #0
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; CHECK-NEXT: cmla z25.s, z5.s, z1.s, #0
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; CHECK-NEXT: cmla z27.s, z6.s, z2.s, #0
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; CHECK-NEXT: cmla z26.s, z7.s, z3.s, #0
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; CHECK-NEXT: cmla z24.s, z4.s, z0.s, #90
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; CHECK-NEXT: cmla z25.s, z5.s, z1.s, #90
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; CHECK-NEXT: cmla z27.s, z6.s, z2.s, #90
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; CHECK-NEXT: cmla z26.s, z7.s, z3.s, #90
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; CHECK-NEXT: mov z0.d, z24.d
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; CHECK-NEXT: mov z1.d, z25.d
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; CHECK-NEXT: mov z2.d, z27.d
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; CHECK-NEXT: mov z3.d, z26.d
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; CHECK-NEXT: ret
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entry:
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%a.deinterleaved = tail call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32> %a)
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%a.real = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %a.deinterleaved, 0
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%a.imag = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %a.deinterleaved, 1
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%b.deinterleaved = tail call { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32> %b)
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%b.real = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %b.deinterleaved, 0
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%b.imag = extractvalue { <vscale x 8 x i32>, <vscale x 8 x i32> } %b.deinterleaved, 1
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%0 = mul <vscale x 8 x i32> %b.imag, %a.real
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%1 = mul <vscale x 8 x i32> %b.real, %a.imag
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%2 = add <vscale x 8 x i32> %1, %0
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%3 = mul <vscale x 8 x i32> %b.real, %a.real
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%4 = mul <vscale x 8 x i32> %a.imag, %b.imag
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%5 = sub <vscale x 8 x i32> %3, %4
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%interleaved.vec = tail call <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32> %5, <vscale x 8 x i32> %2)
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ret <vscale x 16 x i32> %interleaved.vec
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}
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declare { <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave2.nxv4i32(<vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.vector.interleave2.nxv4i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
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declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>)
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declare <vscale x 8 x i32> @llvm.vector.interleave2.nxv8i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare { <vscale x 8 x i32>, <vscale x 8 x i32> } @llvm.vector.deinterleave2.nxv16i32(<vscale x 16 x i32>)
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declare <vscale x 16 x i32> @llvm.vector.interleave2.nxv16i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
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