derek.holloway
7502bf64a4
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147 lines
7.6 KiB
LLVM
147 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s --mattr=+sve2 -o - | FileCheck %s
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target triple = "aarch64"
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; Expected to transform
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define <vscale x 2 x i64> @complex_mul_v2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: complex_mul_v2i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v2.2d, #0000000000000000
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; CHECK-NEXT: cmla z2.d, z1.d, z0.d, #0
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; CHECK-NEXT: cmla z2.d, z1.d, z0.d, #90
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; CHECK-NEXT: mov z0.d, z2.d
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; CHECK-NEXT: ret
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entry:
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%a.deinterleaved = tail call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.vector.deinterleave2.nxv2i64(<vscale x 2 x i64> %a)
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%a.real = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } %a.deinterleaved, 0
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%a.imag = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } %a.deinterleaved, 1
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%b.deinterleaved = tail call { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.vector.deinterleave2.nxv2i64(<vscale x 2 x i64> %b)
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%b.real = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } %b.deinterleaved, 0
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%b.imag = extractvalue { <vscale x 1 x i64>, <vscale x 1 x i64> } %b.deinterleaved, 1
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%0 = mul <vscale x 1 x i64> %b.imag, %a.real
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%1 = mul <vscale x 1 x i64> %b.real, %a.imag
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%2 = add <vscale x 1 x i64> %1, %0
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%3 = mul <vscale x 1 x i64> %b.real, %a.real
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%4 = mul <vscale x 1 x i64> %a.imag, %b.imag
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%5 = sub <vscale x 1 x i64> %3, %4
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%interleaved.vec = tail call <vscale x 2 x i64> @llvm.vector.interleave2.nxv2i64(<vscale x 1 x i64> %5, <vscale x 1 x i64> %2)
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ret <vscale x 2 x i64> %interleaved.vec
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}
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; Expected to transform
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define <vscale x 4 x i64> @complex_mul_v4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
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; CHECK-LABEL: complex_mul_v4i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v4.2d, #0000000000000000
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; CHECK-NEXT: movi v5.2d, #0000000000000000
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; CHECK-NEXT: cmla z5.d, z2.d, z0.d, #0
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; CHECK-NEXT: cmla z4.d, z3.d, z1.d, #0
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; CHECK-NEXT: cmla z5.d, z2.d, z0.d, #90
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; CHECK-NEXT: cmla z4.d, z3.d, z1.d, #90
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; CHECK-NEXT: mov z0.d, z5.d
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; CHECK-NEXT: mov z1.d, z4.d
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; CHECK-NEXT: ret
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entry:
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%a.deinterleaved = tail call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %a)
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%a.real = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %a.deinterleaved, 0
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%a.imag = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %a.deinterleaved, 1
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%b.deinterleaved = tail call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64> %b)
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%b.real = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %b.deinterleaved, 0
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%b.imag = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %b.deinterleaved, 1
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%0 = mul <vscale x 2 x i64> %b.imag, %a.real
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%1 = mul <vscale x 2 x i64> %b.real, %a.imag
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%2 = add <vscale x 2 x i64> %1, %0
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%3 = mul <vscale x 2 x i64> %b.real, %a.real
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%4 = mul <vscale x 2 x i64> %a.imag, %b.imag
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%5 = sub <vscale x 2 x i64> %3, %4
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%interleaved.vec = tail call <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %2)
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ret <vscale x 4 x i64> %interleaved.vec
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}
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; Expected to transform
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define <vscale x 8 x i64> @complex_mul_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
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; CHECK-LABEL: complex_mul_v8i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v24.2d, #0000000000000000
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; CHECK-NEXT: movi v25.2d, #0000000000000000
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; CHECK-NEXT: movi v26.2d, #0000000000000000
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; CHECK-NEXT: movi v27.2d, #0000000000000000
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; CHECK-NEXT: cmla z24.d, z4.d, z0.d, #0
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; CHECK-NEXT: cmla z25.d, z5.d, z1.d, #0
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; CHECK-NEXT: cmla z27.d, z6.d, z2.d, #0
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; CHECK-NEXT: cmla z26.d, z7.d, z3.d, #0
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; CHECK-NEXT: cmla z24.d, z4.d, z0.d, #90
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; CHECK-NEXT: cmla z25.d, z5.d, z1.d, #90
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; CHECK-NEXT: cmla z27.d, z6.d, z2.d, #90
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; CHECK-NEXT: cmla z26.d, z7.d, z3.d, #90
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; CHECK-NEXT: mov z0.d, z24.d
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; CHECK-NEXT: mov z1.d, z25.d
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; CHECK-NEXT: mov z2.d, z27.d
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; CHECK-NEXT: mov z3.d, z26.d
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; CHECK-NEXT: ret
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entry:
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%a.deinterleaved = tail call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %a)
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%a.real = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %a.deinterleaved, 0
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%a.imag = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %a.deinterleaved, 1
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%b.deinterleaved = tail call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %b)
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%b.real = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %b.deinterleaved, 0
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%b.imag = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %b.deinterleaved, 1
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%0 = mul <vscale x 4 x i64> %b.imag, %a.real
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%1 = mul <vscale x 4 x i64> %b.real, %a.imag
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%2 = add <vscale x 4 x i64> %1, %0
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%3 = mul <vscale x 4 x i64> %b.real, %a.real
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%4 = mul <vscale x 4 x i64> %a.imag, %b.imag
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%5 = sub <vscale x 4 x i64> %3, %4
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%interleaved.vec = tail call <vscale x 8 x i64> @llvm.vector.interleave2.nxv8i64(<vscale x 4 x i64> %5, <vscale x 4 x i64> %2)
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ret <vscale x 8 x i64> %interleaved.vec
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}
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; Expected to transform
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define <vscale x 8 x i64> @complex_minus_mul_v8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
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; CHECK-LABEL: complex_minus_mul_v8i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v24.2d, #0000000000000000
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; CHECK-NEXT: movi v25.2d, #0000000000000000
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; CHECK-NEXT: movi v26.2d, #0000000000000000
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; CHECK-NEXT: movi v27.2d, #0000000000000000
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; CHECK-NEXT: cmla z24.d, z4.d, z0.d, #270
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; CHECK-NEXT: cmla z25.d, z5.d, z1.d, #270
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; CHECK-NEXT: cmla z27.d, z6.d, z2.d, #270
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; CHECK-NEXT: cmla z26.d, z7.d, z3.d, #270
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; CHECK-NEXT: cmla z24.d, z4.d, z0.d, #180
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; CHECK-NEXT: cmla z25.d, z5.d, z1.d, #180
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; CHECK-NEXT: cmla z27.d, z6.d, z2.d, #180
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; CHECK-NEXT: cmla z26.d, z7.d, z3.d, #180
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; CHECK-NEXT: mov z0.d, z24.d
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; CHECK-NEXT: mov z1.d, z25.d
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; CHECK-NEXT: mov z2.d, z27.d
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; CHECK-NEXT: mov z3.d, z26.d
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; CHECK-NEXT: ret
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entry:
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%a.deinterleaved = tail call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %a)
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%a.real = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %a.deinterleaved, 0
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%a.imag = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %a.deinterleaved, 1
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%0 = sub <vscale x 4 x i64> zeroinitializer, %a.real
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%b.deinterleaved = tail call { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %b)
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%b.real = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %b.deinterleaved, 0
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%b.imag = extractvalue { <vscale x 4 x i64>, <vscale x 4 x i64> } %b.deinterleaved, 1
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%1 = mul <vscale x 4 x i64> %b.real, %0
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%2 = mul <vscale x 4 x i64> %b.imag, %a.imag
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%3 = add <vscale x 4 x i64> %2, %1
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%4 = mul <vscale x 4 x i64> %b.real, %a.imag
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%5 = mul <vscale x 4 x i64> %b.imag, %0
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%6 = sub <vscale x 4 x i64> %5, %4
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%interleaved.vec = tail call <vscale x 8 x i64> @llvm.vector.interleave2.nxv8i64(<vscale x 4 x i64> %3, <vscale x 4 x i64> %6)
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ret <vscale x 8 x i64> %interleaved.vec
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}
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declare { <vscale x 1 x i64>, <vscale x 1 x i64> } @llvm.vector.deinterleave2.nxv2i64(<vscale x 2 x i64>)
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declare <vscale x 2 x i64> @llvm.vector.interleave2.nxv2i64(<vscale x 1 x i64>, <vscale x 1 x i64>)
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declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>)
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declare <vscale x 4 x i64> @llvm.vector.interleave2.nxv4i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare { <vscale x 4 x i64>, <vscale x 4 x i64> } @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64>)
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declare <vscale x 8 x i64> @llvm.vector.interleave2.nxv8i64(<vscale x 4 x i64>, <vscale x 4 x i64>)
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