derek.holloway
7502bf64a4
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151 lines
6.7 KiB
LLVM
151 lines
6.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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define i16 @combine_add_16xi16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o, i16 %p) {
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; CHECK-LABEL: combine_add_16xi16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: ldr h1, [sp]
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; CHECK-NEXT: add x8, sp, #8
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; CHECK-NEXT: ld1 { v1.h }[1], [x8]
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; CHECK-NEXT: add x8, sp, #16
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; CHECK-NEXT: mov v0.h[1], w1
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; CHECK-NEXT: ld1 { v1.h }[2], [x8]
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; CHECK-NEXT: add x8, sp, #24
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; CHECK-NEXT: mov v0.h[2], w2
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; CHECK-NEXT: ld1 { v1.h }[3], [x8]
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; CHECK-NEXT: add x8, sp, #32
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; CHECK-NEXT: mov v0.h[3], w3
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; CHECK-NEXT: ld1 { v1.h }[4], [x8]
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; CHECK-NEXT: add x8, sp, #40
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; CHECK-NEXT: ld1 { v1.h }[5], [x8]
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; CHECK-NEXT: add x8, sp, #48
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; CHECK-NEXT: mov v0.h[4], w4
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; CHECK-NEXT: ld1 { v1.h }[6], [x8]
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; CHECK-NEXT: add x8, sp, #56
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; CHECK-NEXT: mov v0.h[5], w5
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; CHECK-NEXT: ld1 { v1.h }[7], [x8]
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; CHECK-NEXT: mov v0.h[6], w6
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; CHECK-NEXT: mov v0.h[7], w7
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; CHECK-NEXT: uzp2 v2.16b, v0.16b, v1.16b
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; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: uhadd v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: uaddlv h0, v0.16b
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; CHECK-NEXT: umov w0, v0.h[0]
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; CHECK-NEXT: ret
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%a1 = insertelement <16 x i16> poison, i16 %a, i16 0
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%b1 = insertelement <16 x i16> %a1, i16 %b, i16 1
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%c1 = insertelement <16 x i16> %b1, i16 %c, i16 2
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%d1 = insertelement <16 x i16> %c1, i16 %d, i16 3
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%e1 = insertelement <16 x i16> %d1, i16 %e, i16 4
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%f1 = insertelement <16 x i16> %e1, i16 %f, i16 5
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%g1 = insertelement <16 x i16> %f1, i16 %g, i16 6
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%h1 = insertelement <16 x i16> %g1, i16 %h, i16 7
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%i1 = insertelement <16 x i16> %h1, i16 %i, i16 8
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%j1 = insertelement <16 x i16> %i1, i16 %j, i16 9
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%k1 = insertelement <16 x i16> %j1, i16 %k, i16 10
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%l1 = insertelement <16 x i16> %k1, i16 %l, i16 11
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%m1 = insertelement <16 x i16> %l1, i16 %m, i16 12
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%n1 = insertelement <16 x i16> %m1, i16 %n, i16 13
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%o1 = insertelement <16 x i16> %n1, i16 %o, i16 14
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%p1 = insertelement <16 x i16> %o1, i16 %p, i16 15
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%x = and <16 x i16> %p1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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%sh1 = lshr <16 x i16> %p1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%s = add nuw nsw <16 x i16> %x, %sh1
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%sh2 = lshr <16 x i16> %s, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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%res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %sh2)
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ret i16 %res
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}
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define i32 @combine_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) local_unnamed_addr #0 {
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; CHECK-LABEL: combine_add_8xi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: fmov s1, w4
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; CHECK-NEXT: mov v1.s[1], w5
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; CHECK-NEXT: mov v0.s[1], w1
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; CHECK-NEXT: mov v1.s[2], w6
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; CHECK-NEXT: mov v0.s[2], w2
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; CHECK-NEXT: mov v1.s[3], w7
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; CHECK-NEXT: mov v0.s[3], w3
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; CHECK-NEXT: uzp2 v2.8h, v0.8h, v1.8h
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: uhadd v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: uaddlv s0, v0.8h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%a1 = insertelement <8 x i32> poison, i32 %a, i32 0
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%b1 = insertelement <8 x i32> %a1, i32 %b, i32 1
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%c1 = insertelement <8 x i32> %b1, i32 %c, i32 2
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%d1 = insertelement <8 x i32> %c1, i32 %d, i32 3
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%e1 = insertelement <8 x i32> %d1, i32 %e, i32 4
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%f1 = insertelement <8 x i32> %e1, i32 %f, i32 5
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%g1 = insertelement <8 x i32> %f1, i32 %g, i32 6
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%h1 = insertelement <8 x i32> %g1, i32 %h, i32 7
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%x = and <8 x i32> %h1, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
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%sh1 = lshr <8 x i32> %h1, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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%s = add nuw nsw <8 x i32> %x, %sh1
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%sh2 = lshr <8 x i32> %s, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2)
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ret i32 %res
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}
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define i32 @combine_undef_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 {
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; CHECK-LABEL: combine_undef_add_8xi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s1, w0
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; CHECK-NEXT: dup v0.4s, w8
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; CHECK-NEXT: mov v1.s[1], w1
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; CHECK-NEXT: mov v1.s[2], w2
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; CHECK-NEXT: mov v1.s[3], w3
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; CHECK-NEXT: uzp2 v2.8h, v1.8h, v0.8h
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; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: uhadd v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: uaddlv s0, v0.8h
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%a1 = insertelement <8 x i32> poison, i32 %a, i32 0
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%b1 = insertelement <8 x i32> %a1, i32 %b, i32 1
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%c1 = insertelement <8 x i32> %b1, i32 %c, i32 2
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%d1 = insertelement <8 x i32> %c1, i32 %d, i32 3
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%e1 = insertelement <8 x i32> %d1, i32 undef, i32 4
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%f1 = insertelement <8 x i32> %e1, i32 undef, i32 5
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%g1 = insertelement <8 x i32> %f1, i32 undef, i32 6
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%h1 = insertelement <8 x i32> %g1, i32 undef, i32 7
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%x = and <8 x i32> %h1, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
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%sh1 = lshr <8 x i32> %h1, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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%s = add nuw nsw <8 x i32> %x, %sh1
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%sh2 = lshr <8 x i32> %s, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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%res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2)
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ret i32 %res
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}
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define i64 @combine_add_4xi64(i64 %a, i64 %b, i64 %c, i64 %d) local_unnamed_addr #0 {
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; CHECK-LABEL: combine_add_4xi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d0, x2
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; CHECK-NEXT: fmov d1, x0
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; CHECK-NEXT: mov v0.d[1], x3
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; CHECK-NEXT: mov v1.d[1], x1
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; CHECK-NEXT: uzp2 v2.4s, v1.4s, v0.4s
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; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: uhadd v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: uaddlv d0, v0.4s
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%a1 = insertelement <4 x i64> poison, i64 %a, i64 0
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%b1 = insertelement <4 x i64> %a1, i64 %b, i64 1
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%c1 = insertelement <4 x i64> %b1, i64 %c, i64 2
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%d1 = insertelement <4 x i64> %c1, i64 %d, i64 3
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%x = and <4 x i64> %d1, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
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%sh1 = lshr <4 x i64> %d1, <i64 32, i64 32, i64 32, i64 32>
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%s = add nuw nsw <4 x i64> %x, %sh1
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%sh2 = lshr <4 x i64> %s, <i64 1, i64 1, i64 1, i64 1>
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%res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %sh2)
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ret i64 %res
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}
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declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)
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declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
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declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
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