derek/TheRock
1
0 Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
1a182e2dac58879f215c0fad0f5f78c76dcafe56
TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/dup-ext-load-combine.ll
T
derek.holloway 7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
Details
CodeQL / Analyze (python) (push) Canceled after 0s
Details
pre-commit / pre-commit (push) Canceled after 0s
Details
Multi-Arch CI / setup (push) Canceled after 0s
Details
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Details
Setup (Multi-Arch) / setup (push) Canceled after 0s
Details
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Details
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
Details
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Details
Multi-Arch CI / CI Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Details
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
Details
Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

179 lines
6.2 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
; Test optimization of DUP with extended narrow loads
; This should avoid GPR->SIMD transfers by loading directly into vector registers
define <4 x i16> @test_dup_zextload_i8_v4i16(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i8_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0]
; CHECK-NEXT: dup v0.4h, v0.h[0]
; CHECK-NEXT: ret
%load = load i8, ptr %p, align 1
%ext = zext i8 %load to i16
%vec = insertelement <4 x i16> poison, i16 %ext, i32 0
%dup = shufflevector <4 x i16> %vec, <4 x i16> poison, <4 x i32> zeroinitializer
ret <4 x i16> %dup
}
define <8 x i16> @test_dup_zextload_i8_v8i16(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i8_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0]
; CHECK-NEXT: dup v0.8h, v0.h[0]
; CHECK-NEXT: ret
%load = load i8, ptr %p, align 1
%ext = zext i8 %load to i16
%vec = insertelement <8 x i16> poison, i16 %ext, i32 0
%dup = shufflevector <8 x i16> %vec, <8 x i16> poison, <8 x i32> zeroinitializer
ret <8 x i16> %dup
}
define <2 x i32> @test_dup_zextload_i8_v2i32(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i8_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0]
; CHECK-NEXT: dup v0.2s, v0.s[0]
; CHECK-NEXT: ret
%load = load i8, ptr %p, align 1
%ext = zext i8 %load to i32
%vec = insertelement <2 x i32> poison, i32 %ext, i32 0
%dup = shufflevector <2 x i32> %vec, <2 x i32> poison, <2 x i32> zeroinitializer
ret <2 x i32> %dup
}
define <4 x i32> @test_dup_zextload_i8_v4i32(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i8_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0]
; CHECK-NEXT: dup v0.4s, v0.s[0]
; CHECK-NEXT: ret
%load = load i8, ptr %p, align 1
%ext = zext i8 %load to i32
%vec = insertelement <4 x i32> poison, i32 %ext, i32 0
%dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer
ret <4 x i32> %dup
}
define <4 x i32> @test_dup_zextload_i8_v4i32_offset(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i8_v4i32_offset:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0, #4]
; CHECK-NEXT: dup v0.4s, v0.s[0]
; CHECK-NEXT: ret
%addr = getelementptr inbounds i8, ptr %p, i64 4
%load = load i8, ptr %addr, align 1
%ext = zext i8 %load to i32
%vec = insertelement <4 x i32> poison, i32 %ext, i32 0
%dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer
ret <4 x i32> %dup
}
define <4 x i32> @test_dup_zextload_i8_v4i32_reg_offset(ptr %p, i64 %offset) {
; CHECK-LABEL: test_dup_zextload_i8_v4i32_reg_offset:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0, x1]
; CHECK-NEXT: dup v0.4s, v0.s[0]
; CHECK-NEXT: ret
%addr = getelementptr inbounds i8, ptr %p, i64 %offset
%load = load i8, ptr %addr, align 1
%ext = zext i8 %load to i32
%vec = insertelement <4 x i32> poison, i32 %ext, i32 0
%dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer
ret <4 x i32> %dup
}
define <2 x i64> @test_dup_zextload_i8_v2i64(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i8_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0]
; CHECK-NEXT: dup v0.2d, v0.d[0]
; CHECK-NEXT: ret
%load = load i8, ptr %p, align 1
%ext = zext i8 %load to i64
%vec = insertelement <2 x i64> poison, i64 %ext, i32 0
%dup = shufflevector <2 x i64> %vec, <2 x i64> poison, <2 x i32> zeroinitializer
ret <2 x i64> %dup
}
define <2 x i32> @test_dup_zextload_i16_v2i32(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i16_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x0]
; CHECK-NEXT: dup v0.2s, v0.s[0]
; CHECK-NEXT: ret
%load = load i16, ptr %p, align 1
%ext = zext i16 %load to i32
%vec = insertelement <2 x i32> poison, i32 %ext, i32 0
%dup = shufflevector <2 x i32> %vec, <2 x i32> poison, <2 x i32> zeroinitializer
ret <2 x i32> %dup
}
define <4 x i32> @test_dup_zextload_i16_v4i32(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i16_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x0]
; CHECK-NEXT: dup v0.4s, v0.s[0]
; CHECK-NEXT: ret
%load = load i16, ptr %p, align 1
%ext = zext i16 %load to i32
%vec = insertelement <4 x i32> poison, i32 %ext, i32 0
%dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer
ret <4 x i32> %dup
}
define <4 x i32> @test_dup_zextload_i16_v4i32_offset(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i16_v4i32_offset:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x0, #8]
; CHECK-NEXT: dup v0.4s, v0.s[0]
; CHECK-NEXT: ret
%addr = getelementptr inbounds i16, ptr %p, i64 4
%load = load i16, ptr %addr, align 1
%ext = zext i16 %load to i32
%vec = insertelement <4 x i32> poison, i32 %ext, i32 0
%dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer
ret <4 x i32> %dup
}
define <4 x i32> @test_dup_zextload_i16_v4i32_reg_offset(ptr %p, i64 %offset) {
; CHECK-LABEL: test_dup_zextload_i16_v4i32_reg_offset:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x0, x1, lsl #1]
; CHECK-NEXT: dup v0.4s, v0.s[0]
; CHECK-NEXT: ret
%addr = getelementptr inbounds i16, ptr %p, i64 %offset
%load = load i16, ptr %addr, align 1
%ext = zext i16 %load to i32
%vec = insertelement <4 x i32> poison, i32 %ext, i32 0
%dup = shufflevector <4 x i32> %vec, <4 x i32> poison, <4 x i32> zeroinitializer
ret <4 x i32> %dup
}
define <2 x i64> @test_dup_zextload_i16_v2i64(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i16_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x0]
; CHECK-NEXT: dup v0.2d, v0.d[0]
; CHECK-NEXT: ret
%load = load i16, ptr %p, align 1
%ext = zext i16 %load to i64
%vec = insertelement <2 x i64> poison, i64 %ext, i32 0
%dup = shufflevector <2 x i64> %vec, <2 x i64> poison, <2 x i32> zeroinitializer
ret <2 x i64> %dup
}
define <2 x i64> @test_dup_zextload_i32_v2i64(ptr %p) {
; CHECK-LABEL: test_dup_zextload_i32_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr s0, [x0]
; CHECK-NEXT: dup v0.2d, v0.d[0]
; CHECK-NEXT: ret
%load = load i32, ptr %p, align 1
%ext = zext i32 %load to i64
%vec = insertelement <2 x i64> poison, i64 %ext, i32 0
%dup = shufflevector <2 x i64> %vec, <2 x i64> poison, <2 x i32> zeroinitializer
ret <2 x i64> %dup
}
Reference in new issue View Git Blame Copy Permalink