derek.holloway
7502bf64a4
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329 lines
11 KiB
LLVM
329 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,SIGNED-ZEROS
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; RUN: llc -mtriple=aarch64 --enable-no-signed-zeros-fp-math < %s | FileCheck %s --check-prefixes=CHECK,NO-SIGNED-ZEROS
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; Test folding of float->int->float roundtrips into float-only operations.
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; The optimization could converts patterns like:
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; sitofp(fptosi(x)) -> ftrunc(x)
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; sitofp(smin(fptosi(x), C)) -> fminnum(ftrunc(x), (float)C)
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; This is relevant for AArch64 as it avoids GPR bouncing and keeps computation in SIMD/FP registers.
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define float @test_signed_basic(float %x) {
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; SIGNED-ZEROS-LABEL: test_signed_basic:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: fcvtzs s0, s0
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; SIGNED-ZEROS-NEXT: scvtf s0, s0
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_signed_basic:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptosi float %x to i32
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%f = sitofp i32 %i to float
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ret float %f
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}
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define float @test_unsigned_basic(float %x) {
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; SIGNED-ZEROS-LABEL: test_unsigned_basic:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: fcvtzu s0, s0
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; SIGNED-ZEROS-NEXT: ucvtf s0, s0
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_unsigned_basic:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptoui float %x to i32
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%f = uitofp i32 %i to float
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ret float %f
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}
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define float @test_signed_min_max(float %x) {
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; SIGNED-ZEROS-LABEL: test_signed_min_max:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: fcvtzs w9, s0
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; SIGNED-ZEROS-NEXT: mov w8, #-512 // =0xfffffe00
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; SIGNED-ZEROS-NEXT: cmn w9, #512
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; SIGNED-ZEROS-NEXT: csel w8, w9, w8, gt
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; SIGNED-ZEROS-NEXT: mov w9, #1023 // =0x3ff
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; SIGNED-ZEROS-NEXT: cmp w8, #1023
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; SIGNED-ZEROS-NEXT: csel w8, w8, w9, lt
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; SIGNED-ZEROS-NEXT: scvtf s0, w8
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_signed_min_max:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: movi v1.2s, #196, lsl #24
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; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
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; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
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; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
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; NO-SIGNED-ZEROS-NEXT: fmaxnm s0, s0, s1
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; NO-SIGNED-ZEROS-NEXT: fmov s1, w8
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; NO-SIGNED-ZEROS-NEXT: fminnm s0, s0, s1
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptosi float %x to i32
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%lower = call i32 @llvm.smax.i32(i32 %i, i32 -512)
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%clamped = call i32 @llvm.smin.i32(i32 %lower, i32 1023)
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%f = sitofp i32 %clamped to float
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ret float %f
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}
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define float @test_unsigned_min_max(float %x) {
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; SIGNED-ZEROS-LABEL: test_unsigned_min_max:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: fcvtzu w9, s0
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; SIGNED-ZEROS-NEXT: mov w8, #512 // =0x200
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; SIGNED-ZEROS-NEXT: cmp w9, #512
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; SIGNED-ZEROS-NEXT: csel w8, w9, w8, hi
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; SIGNED-ZEROS-NEXT: mov w9, #1023 // =0x3ff
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; SIGNED-ZEROS-NEXT: cmp w8, #1023
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; SIGNED-ZEROS-NEXT: csel w8, w8, w9, lo
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; SIGNED-ZEROS-NEXT: ucvtf s0, w8
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_unsigned_min_max:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: movi v1.2s, #68, lsl #24
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; NO-SIGNED-ZEROS-NEXT: frintz s0, s0
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; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
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; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
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; NO-SIGNED-ZEROS-NEXT: fmaxnm s0, s0, s1
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; NO-SIGNED-ZEROS-NEXT: fmov s1, w8
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; NO-SIGNED-ZEROS-NEXT: fminnm s0, s0, s1
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptoui float %x to i32
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%lower = call i32 @llvm.umax.i32(i32 %i, i32 512)
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%clamped = call i32 @llvm.umin.i32(i32 %lower, i32 1023)
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%f = uitofp i32 %clamped to float
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ret float %f
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}
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; 16777217 is NOT exactly representable in f32.
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define float @test_inexact_16777217(float %x) {
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; CHECK-LABEL: test_inexact_16777217:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs w8, s0
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; CHECK-NEXT: mov w9, #16777216 // =0x1000000
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: mov w9, #1 // =0x1
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; CHECK-NEXT: movk w9, #256, lsl #16
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; CHECK-NEXT: csel w8, w8, w9, le
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; CHECK-NEXT: scvtf s0, w8
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; CHECK-NEXT: ret
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entry:
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%i = fptosi float %x to i32
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%clamped = call i32 @llvm.smin.i32(i32 %i, i32 16777217)
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%f = sitofp i32 %clamped to float
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ret float %f
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}
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define <4 x float> @test_signed_v4f32(<4 x float> %x) {
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; SIGNED-ZEROS-LABEL: test_signed_v4f32:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: fcvtzs v0.4s, v0.4s
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; SIGNED-ZEROS-NEXT: scvtf v0.4s, v0.4s
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_signed_v4f32:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptosi <4 x float> %x to <4 x i32>
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%f = sitofp <4 x i32> %i to <4 x float>
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ret <4 x float> %f
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}
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define <4 x float> @test_unsigned_v4f32(<4 x float> %x) {
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; SIGNED-ZEROS-LABEL: test_unsigned_v4f32:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: fcvtzu v0.4s, v0.4s
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; SIGNED-ZEROS-NEXT: ucvtf v0.4s, v0.4s
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_unsigned_v4f32:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptoui <4 x float> %x to <4 x i32>
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%f = uitofp <4 x i32> %i to <4 x float>
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ret <4 x float> %f
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}
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define <2 x double> @test_signed_v2f64(<2 x double> %x) {
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; SIGNED-ZEROS-LABEL: test_signed_v2f64:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: fcvtzs v0.2d, v0.2d
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; SIGNED-ZEROS-NEXT: scvtf v0.2d, v0.2d
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_signed_v2f64:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: frintz v0.2d, v0.2d
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptosi <2 x double> %x to <2 x i64>
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%f = sitofp <2 x i64> %i to <2 x double>
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ret <2 x double> %f
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}
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define <2 x double> @test_unsigned_v2f64(<2 x double> %x) {
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; SIGNED-ZEROS-LABEL: test_unsigned_v2f64:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: fcvtzu v0.2d, v0.2d
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; SIGNED-ZEROS-NEXT: ucvtf v0.2d, v0.2d
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_unsigned_v2f64:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: frintz v0.2d, v0.2d
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptoui <2 x double> %x to <2 x i64>
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%f = uitofp <2 x i64> %i to <2 x double>
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ret <2 x double> %f
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}
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define <4 x float> @test_signed_v4f32_min_max(<4 x float> %x) {
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; SIGNED-ZEROS-LABEL: test_signed_v4f32_min_max:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: fcvtzs v0.4s, v0.4s
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; SIGNED-ZEROS-NEXT: mvni v1.4s, #1, msl #8
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; SIGNED-ZEROS-NEXT: movi v2.4s, #3, msl #8
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; SIGNED-ZEROS-NEXT: smax v0.4s, v0.4s, v1.4s
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; SIGNED-ZEROS-NEXT: smin v0.4s, v0.4s, v2.4s
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; SIGNED-ZEROS-NEXT: scvtf v0.4s, v0.4s
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_signed_v4f32_min_max:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: movi v1.4s, #196, lsl #24
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; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
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; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
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; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
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; NO-SIGNED-ZEROS-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
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; NO-SIGNED-ZEROS-NEXT: dup v1.4s, w8
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; NO-SIGNED-ZEROS-NEXT: fminnm v0.4s, v0.4s, v1.4s
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptosi <4 x float> %x to <4 x i32>
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%lower = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 -512))
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%clamped = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %lower, <4 x i32> splat (i32 1023))
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%f = sitofp <4 x i32> %clamped to <4 x float>
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ret <4 x float> %f
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}
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define <4 x float> @test_unsigned_v4f32_min_max(<4 x float> %x) {
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; SIGNED-ZEROS-LABEL: test_unsigned_v4f32_min_max:
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; SIGNED-ZEROS: // %bb.0: // %entry
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; SIGNED-ZEROS-NEXT: movi v1.4s, #2, lsl #8
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; SIGNED-ZEROS-NEXT: fcvtzu v0.4s, v0.4s
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; SIGNED-ZEROS-NEXT: movi v2.4s, #3, msl #8
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; SIGNED-ZEROS-NEXT: umax v0.4s, v0.4s, v1.4s
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; SIGNED-ZEROS-NEXT: umin v0.4s, v0.4s, v2.4s
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; SIGNED-ZEROS-NEXT: ucvtf v0.4s, v0.4s
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; SIGNED-ZEROS-NEXT: ret
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;
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; NO-SIGNED-ZEROS-LABEL: test_unsigned_v4f32_min_max:
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; NO-SIGNED-ZEROS: // %bb.0: // %entry
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; NO-SIGNED-ZEROS-NEXT: movi v1.4s, #68, lsl #24
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; NO-SIGNED-ZEROS-NEXT: frintz v0.4s, v0.4s
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; NO-SIGNED-ZEROS-NEXT: mov w8, #49152 // =0xc000
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; NO-SIGNED-ZEROS-NEXT: movk w8, #17535, lsl #16
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; NO-SIGNED-ZEROS-NEXT: fmaxnm v0.4s, v0.4s, v1.4s
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; NO-SIGNED-ZEROS-NEXT: dup v1.4s, w8
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; NO-SIGNED-ZEROS-NEXT: fminnm v0.4s, v0.4s, v1.4s
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; NO-SIGNED-ZEROS-NEXT: ret
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entry:
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%i = fptoui <4 x float> %x to <4 x i32>
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%lower = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %i, <4 x i32> splat (i32 512))
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%clamped = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %lower, <4 x i32> splat (i32 1023))
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%f = uitofp <4 x i32> %clamped to <4 x float>
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ret <4 x float> %f
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}
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define i1 @test_fcmp(float %x) {
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; CHECK-LABEL: test_fcmp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintz s0, s0
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; CHECK-NEXT: fcmp s0, #0.0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%conv1 = fptosi float %x to i32
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%conv2 = sitofp i32 %conv1 to float
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%cmp = fcmp oeq float %conv2, 0.0
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ret i1 %cmp
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}
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define float @test_fabs(float %x) {
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; CHECK-LABEL: test_fabs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintz s0, s0
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; CHECK-NEXT: fabs s0, s0
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; CHECK-NEXT: ret
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%conv1 = fptosi float %x to i32
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%conv2 = sitofp i32 %conv1 to float
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%abs = call float @llvm.fabs.f32(float %conv2)
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ret float %abs
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}
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define float @test_copysign(float %x, float %y) {
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; CHECK-LABEL: test_copysign:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintz s0, s0
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; CHECK-NEXT: mvni v2.4s, #128, lsl #24
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; CHECK-NEXT: // kill: def $s1 killed $s1 def $q1
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: ret
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%conv1 = fptosi float %x to i32
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%conv2 = sitofp i32 %conv1 to float
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%combine = call float @llvm.copysign.f32(float %conv2, float %y)
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ret float %combine
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}
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define float @test_fadd(float %x) {
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; CHECK-LABEL: test_fadd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintz s0, s0
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; CHECK-NEXT: fmov s1, #1.00000000
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: ret
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%conv1 = fptosi float %x to i32
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%conv2 = sitofp i32 %conv1 to float
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%add = fadd float %conv2, 1.0
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ret float %add
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}
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define float @test_fsub(float %x) {
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; CHECK-LABEL: test_fsub:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintz s0, s0
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; CHECK-NEXT: fmov s1, #-1.00000000
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; CHECK-NEXT: fadd s0, s0, s1
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; CHECK-NEXT: ret
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%conv1 = fptosi float %x to i32
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%conv2 = sitofp i32 %conv1 to float
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%sub = fsub float %conv2, 1.0
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ret float %sub
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}
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declare i32 @llvm.smin.i32(i32, i32)
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declare i32 @llvm.smax.i32(i32, i32)
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declare i32 @llvm.umin.i32(i32, i32)
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declare i32 @llvm.umax.i32(i32, i32)
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declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
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declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>)
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declare float @llvm.fabs.f32(float)
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declare float @llvm.copysign.f32(float, float)
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