derek.holloway
7502bf64a4
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117 lines
4.3 KiB
LLVM
117 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --disable-replace-with-vec-lib --vector-library=ArmPL < %s -o - | FileCheck --check-prefix=ARMPL %s
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; RUN: llc --disable-replace-with-vec-lib --vector-library=sleefgnuabi < %s -o - | FileCheck --check-prefix=SLEEF %s
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target triple = "aarch64-unknown-linux-gnu"
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define <2 x double> @frem_v2f64(<2 x double> %unused, <2 x double> %a, <2 x double> %b) #0 {
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; ARMPL-LABEL: frem_v2f64:
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; ARMPL: // %bb.0:
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; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; ARMPL-NEXT: .cfi_def_cfa_offset 16
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; ARMPL-NEXT: .cfi_offset w30, -16
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; ARMPL-NEXT: mov v0.16b, v1.16b
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; ARMPL-NEXT: mov v1.16b, v2.16b
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; ARMPL-NEXT: bl armpl_vfmodq_f64
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; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; ARMPL-NEXT: ret
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;
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; SLEEF-LABEL: frem_v2f64:
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; SLEEF: // %bb.0:
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; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; SLEEF-NEXT: .cfi_def_cfa_offset 16
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; SLEEF-NEXT: .cfi_offset w30, -16
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; SLEEF-NEXT: mov v0.16b, v1.16b
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; SLEEF-NEXT: mov v1.16b, v2.16b
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; SLEEF-NEXT: bl _ZGVnN2vv_fmod
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; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; SLEEF-NEXT: ret
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%res = frem <2 x double> %a, %b
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ret <2 x double> %res
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}
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define <4 x float> @frem_strict_v4f32(<4 x float> %unused, <4 x float> %a, <4 x float> %b) #1 {
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; ARMPL-LABEL: frem_strict_v4f32:
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; ARMPL: // %bb.0:
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; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; ARMPL-NEXT: .cfi_def_cfa_offset 16
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; ARMPL-NEXT: .cfi_offset w30, -16
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; ARMPL-NEXT: mov v0.16b, v1.16b
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; ARMPL-NEXT: mov v1.16b, v2.16b
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; ARMPL-NEXT: bl armpl_vfmodq_f32
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; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; ARMPL-NEXT: ret
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;
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; SLEEF-LABEL: frem_strict_v4f32:
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; SLEEF: // %bb.0:
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; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; SLEEF-NEXT: .cfi_def_cfa_offset 16
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; SLEEF-NEXT: .cfi_offset w30, -16
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; SLEEF-NEXT: mov v0.16b, v1.16b
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; SLEEF-NEXT: mov v1.16b, v2.16b
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; SLEEF-NEXT: bl _ZGVnN4vv_fmodf
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; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; SLEEF-NEXT: ret
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%res = frem <4 x float> %a, %b
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ret <4 x float> %res
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}
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define <vscale x 4 x float> @frem_nxv4f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
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; ARMPL-LABEL: frem_nxv4f32:
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; ARMPL: // %bb.0:
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; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; ARMPL-NEXT: .cfi_def_cfa_offset 16
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; ARMPL-NEXT: .cfi_offset w30, -16
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; ARMPL-NEXT: mov z0.d, z1.d
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; ARMPL-NEXT: mov z1.d, z2.d
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; ARMPL-NEXT: ptrue p0.s
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; ARMPL-NEXT: bl armpl_svfmod_f32_x
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; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; ARMPL-NEXT: ret
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;
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; SLEEF-LABEL: frem_nxv4f32:
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; SLEEF: // %bb.0:
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; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; SLEEF-NEXT: .cfi_def_cfa_offset 16
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; SLEEF-NEXT: .cfi_offset w30, -16
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; SLEEF-NEXT: mov z0.d, z1.d
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; SLEEF-NEXT: mov z1.d, z2.d
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; SLEEF-NEXT: ptrue p0.s
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; SLEEF-NEXT: bl _ZGVsMxvv_fmodf
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; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; SLEEF-NEXT: ret
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%res = frem <vscale x 4 x float> %a, %b
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ret <vscale x 4 x float> %res
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}
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define <vscale x 2 x double> @frem_strict_nxv2f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %a, <vscale x 2 x double> %b) #1 {
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; ARMPL-LABEL: frem_strict_nxv2f64:
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; ARMPL: // %bb.0:
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; ARMPL-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; ARMPL-NEXT: .cfi_def_cfa_offset 16
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; ARMPL-NEXT: .cfi_offset w30, -16
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; ARMPL-NEXT: mov z0.d, z1.d
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; ARMPL-NEXT: mov z1.d, z2.d
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; ARMPL-NEXT: ptrue p0.d
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; ARMPL-NEXT: bl armpl_svfmod_f64_x
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; ARMPL-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; ARMPL-NEXT: ret
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;
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; SLEEF-LABEL: frem_strict_nxv2f64:
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; SLEEF: // %bb.0:
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; SLEEF-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
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; SLEEF-NEXT: .cfi_def_cfa_offset 16
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; SLEEF-NEXT: .cfi_offset w30, -16
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; SLEEF-NEXT: mov z0.d, z1.d
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; SLEEF-NEXT: mov z1.d, z2.d
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; SLEEF-NEXT: ptrue p0.d
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; SLEEF-NEXT: bl _ZGVsMxvv_fmod
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; SLEEF-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
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; SLEEF-NEXT: ret
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%res = frem <vscale x 2 x double> %a, %b
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ret <vscale x 2 x double> %res
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}
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attributes #0 = { "target-features"="+sve" }
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attributes #1 = { "target-features"="+sve" strictfp }
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