derek.holloway
7502bf64a4
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115 lines
5.3 KiB
LLVM
115 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mattr=+sve2,+fp8,+fp8fma < %s | FileCheck %s
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; RUN: llc -mattr=+sme,+fp8,+ssve-fp8fma --force-streaming < %s | FileCheck %s
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target triple = "aarch64-linux"
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define <vscale x 8 x half> @fmla_2way_bot(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_2way_bot:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlalb z0.h, z1.b, z2.b
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)
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ret <vscale x 8 x half> %r
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}
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define <vscale x 8 x half> @fmla_2way_top(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_2way_top:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlalt z0.h, z1.b, z2.b
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)
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ret <vscale x 8 x half> %r
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}
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define <vscale x 8 x half> @fmla_2way_bot_lane(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_2way_bot_lane:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlalb z0.h, z1.b, z2.b[3]
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalb.lane.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)
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ret <vscale x 8 x half> %r
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}
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define <vscale x 8 x half> @fmla_2way_top_lane(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_2way_top_lane:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlalt z0.h, z1.b, z2.b[3]
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; CHECK-NEXT: ret
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%r = call <vscale x 8 x half> @llvm.aarch64.sve.fp8.fmlalt.lane.nxv8f16(<vscale x 8 x half> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)
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ret <vscale x 8 x half> %r
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}
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define <vscale x 4 x float> @fmla_4way_bb(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_4way_bb:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlallbb z0.s, z1.b, z2.b
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @fmla_4way_bt(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_4way_bt:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlallbt z0.s, z1.b, z2.b
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbt.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @fmla_4way_tb(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_4way_tb:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlalltb z0.s, z1.b, z2.b
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltb.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @fmla_4way_tt(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_4way_tt:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlalltt z0.s, z1.b, z2.b
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltt.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2)
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @fmla_4way_bb_lane(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_4way_bb_lane:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlallbb z0.s, z1.b, z2.b[3]
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbb.lane.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @fmla_4way_bt_lane(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_4way_bt_lane:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlallbt z0.s, z1.b, z2.b[3]
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlallbt.lane.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @fmla_4way_tb_lane(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_4way_tb_lane:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlalltb z0.s, z1.b, z2.b[3]
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltb.lane.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @fmla_4way_tt_lane(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2) {
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; CHECK-LABEL: fmla_4way_tt_lane:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmlalltt z0.s, z1.b, z2.b[3]
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; CHECK-NEXT: ret
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltt.lane.nxv4f32(<vscale x 4 x float> %a, <vscale x 16 x i8> %s1, <vscale x 16 x i8> %s2, i32 3)
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ret <vscale x 4 x float> %r
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}
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