derek.holloway
7502bf64a4
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3677 lines
156 KiB
LLVM
3677 lines
156 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 -global-isel=0| FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-SD
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; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-SD
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; RUN: llc < %s -mtriple=aarch64 -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT,CHECK-CVT-GI
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; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-FP16-GI
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; i32 saturate
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define <2 x i32> @stest_f64i32(<2 x double> %x) {
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; CHECK-LABEL: stest_f64i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs v0.2d, v0.2d
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; CHECK-NEXT: sqxtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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entry:
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%conv = fptosi <2 x double> %x to <2 x i64>
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%0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647>
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%spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>
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%1 = icmp sgt <2 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648>
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%spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>
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%conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
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ret <2 x i32> %conv6
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}
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define <2 x i32> @utest_f64i32(<2 x double> %x) {
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; CHECK-CVT-SD-LABEL: utest_f64i32:
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; CHECK-CVT-SD: // %bb.0: // %entry
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; CHECK-CVT-SD-NEXT: mov d1, v0.d[1]
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; CHECK-CVT-SD-NEXT: fcvtzu w8, d0
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; CHECK-CVT-SD-NEXT: fcvtzu w9, d1
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; CHECK-CVT-SD-NEXT: fmov s0, w8
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; CHECK-CVT-SD-NEXT: mov v0.s[1], w9
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; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-CVT-SD-NEXT: ret
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;
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; CHECK-FP16-SD-LABEL: utest_f64i32:
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; CHECK-FP16-SD: // %bb.0: // %entry
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; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
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; CHECK-FP16-SD-NEXT: fcvtzu w8, d0
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; CHECK-FP16-SD-NEXT: fcvtzu w9, d1
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; CHECK-FP16-SD-NEXT: fmov s0, w8
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; CHECK-FP16-SD-NEXT: mov v0.s[1], w9
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; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-FP16-SD-NEXT: ret
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;
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; CHECK-CVT-GI-LABEL: utest_f64i32:
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; CHECK-CVT-GI: // %bb.0: // %entry
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; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
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; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
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; CHECK-CVT-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
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; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
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; CHECK-CVT-GI-NEXT: ret
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;
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; CHECK-FP16-GI-LABEL: utest_f64i32:
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; CHECK-FP16-GI: // %bb.0: // %entry
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; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
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; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
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; CHECK-FP16-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
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; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
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; CHECK-FP16-GI-NEXT: ret
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entry:
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%conv = fptoui <2 x double> %x to <2 x i64>
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%0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295>
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%spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>
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%conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>
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ret <2 x i32> %conv6
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}
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define <2 x i32> @ustest_f64i32(<2 x double> %x) {
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; CHECK-LABEL: ustest_f64i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzs v0.2d, v0.2d
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; CHECK-NEXT: sqxtun v0.2s, v0.2d
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; CHECK-NEXT: ret
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entry:
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%conv = fptosi <2 x double> %x to <2 x i64>
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%0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295>
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%spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>
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%1 = icmp sgt <2 x i64> %spec.store.select, zeroinitializer
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%spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> zeroinitializer
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%conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
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ret <2 x i32> %conv6
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}
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define <4 x i32> @stest_f32i32(<4 x float> %x) {
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; CHECK-CVT-SD-LABEL: stest_f32i32:
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; CHECK-CVT-SD: // %bb.0: // %entry
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; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
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; CHECK-CVT-SD-NEXT: ret
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;
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; CHECK-FP16-SD-LABEL: stest_f32i32:
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; CHECK-FP16-SD: // %bb.0: // %entry
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; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
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; CHECK-FP16-SD-NEXT: ret
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;
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; CHECK-CVT-GI-LABEL: stest_f32i32:
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; CHECK-CVT-GI: // %bb.0: // %entry
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; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
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; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
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; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v0.2d
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; CHECK-CVT-GI-NEXT: sqxtn v0.2s, v1.2d
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; CHECK-CVT-GI-NEXT: sqxtn2 v0.4s, v2.2d
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; CHECK-CVT-GI-NEXT: ret
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;
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; CHECK-FP16-GI-LABEL: stest_f32i32:
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; CHECK-FP16-GI: // %bb.0: // %entry
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; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
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; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
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; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v0.2d
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; CHECK-FP16-GI-NEXT: sqxtn v0.2s, v1.2d
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; CHECK-FP16-GI-NEXT: sqxtn2 v0.4s, v2.2d
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; CHECK-FP16-GI-NEXT: ret
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entry:
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%conv = fptosi <4 x float> %x to <4 x i64>
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%0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
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%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
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%1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
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%spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
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%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
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ret <4 x i32> %conv6
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}
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define <4 x i32> @utest_f32i32(<4 x float> %x) {
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; CHECK-LABEL: utest_f32i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtzu v0.4s, v0.4s
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; CHECK-NEXT: ret
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entry:
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%conv = fptoui <4 x float> %x to <4 x i64>
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%0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
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%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
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%conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
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ret <4 x i32> %conv6
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}
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define <4 x i32> @ustest_f32i32(<4 x float> %x) {
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; CHECK-CVT-SD-LABEL: ustest_f32i32:
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; CHECK-CVT-SD: // %bb.0: // %entry
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; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
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; CHECK-CVT-SD-NEXT: ret
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;
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; CHECK-FP16-SD-LABEL: ustest_f32i32:
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; CHECK-FP16-SD: // %bb.0: // %entry
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; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
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; CHECK-FP16-SD-NEXT: ret
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;
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; CHECK-CVT-GI-LABEL: ustest_f32i32:
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; CHECK-CVT-GI: // %bb.0: // %entry
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; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
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; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
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; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v0.2d
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; CHECK-CVT-GI-NEXT: sqxtun v0.2s, v1.2d
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; CHECK-CVT-GI-NEXT: sqxtun2 v0.4s, v2.2d
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; CHECK-CVT-GI-NEXT: ret
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;
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; CHECK-FP16-GI-LABEL: ustest_f32i32:
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; CHECK-FP16-GI: // %bb.0: // %entry
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; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
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; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
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; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v0.2d
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; CHECK-FP16-GI-NEXT: sqxtun v0.2s, v1.2d
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; CHECK-FP16-GI-NEXT: sqxtun2 v0.4s, v2.2d
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; CHECK-FP16-GI-NEXT: ret
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entry:
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%conv = fptosi <4 x float> %x to <4 x i64>
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%0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
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%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
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%1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer
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%spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer
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%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
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ret <4 x i32> %conv6
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}
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define <4 x i32> @stest_f16i32(<4 x half> %x) {
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; CHECK-CVT-SD-LABEL: stest_f16i32:
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; CHECK-CVT-SD: // %bb.0: // %entry
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; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
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; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
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; CHECK-CVT-SD-NEXT: ret
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;
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; CHECK-FP16-SD-LABEL: stest_f16i32:
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; CHECK-FP16-SD: // %bb.0: // %entry
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; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
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; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
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; CHECK-FP16-SD-NEXT: ret
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;
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; CHECK-CVT-GI-LABEL: stest_f16i32:
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; CHECK-CVT-GI: // %bb.0: // %entry
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; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
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; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
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; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
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; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v0.2d
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; CHECK-CVT-GI-NEXT: sqxtn v0.2s, v1.2d
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; CHECK-CVT-GI-NEXT: sqxtn2 v0.4s, v2.2d
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; CHECK-CVT-GI-NEXT: ret
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;
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; CHECK-FP16-GI-LABEL: stest_f16i32:
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; CHECK-FP16-GI: // %bb.0: // %entry
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; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
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; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
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; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
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; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v0.2d
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; CHECK-FP16-GI-NEXT: sqxtn v0.2s, v1.2d
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; CHECK-FP16-GI-NEXT: sqxtn2 v0.4s, v2.2d
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; CHECK-FP16-GI-NEXT: ret
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entry:
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%conv = fptosi <4 x half> %x to <4 x i64>
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%0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
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%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
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%1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
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%spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>
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%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
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ret <4 x i32> %conv6
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}
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define <4 x i32> @utest_f16i32(<4 x half> %x) {
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; CHECK-LABEL: utest_f16i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtl v0.4s, v0.4h
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; CHECK-NEXT: fcvtzu v0.4s, v0.4s
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; CHECK-NEXT: ret
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entry:
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%conv = fptoui <4 x half> %x to <4 x i64>
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%0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
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%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
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%conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
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ret <4 x i32> %conv6
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}
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define <4 x i32> @ustest_f16i32(<4 x half> %x) {
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; CHECK-CVT-SD-LABEL: ustest_f16i32:
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; CHECK-CVT-SD: // %bb.0: // %entry
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; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
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; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
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; CHECK-CVT-SD-NEXT: ret
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;
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; CHECK-FP16-SD-LABEL: ustest_f16i32:
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; CHECK-FP16-SD: // %bb.0: // %entry
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; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
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; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
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; CHECK-FP16-SD-NEXT: ret
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;
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; CHECK-CVT-GI-LABEL: ustest_f16i32:
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; CHECK-CVT-GI: // %bb.0: // %entry
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; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
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; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
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; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
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; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
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; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v0.2d
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; CHECK-CVT-GI-NEXT: sqxtun v0.2s, v1.2d
|
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; CHECK-CVT-GI-NEXT: sqxtun2 v0.4s, v2.2d
|
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; CHECK-CVT-GI-NEXT: ret
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;
|
|
; CHECK-FP16-GI-LABEL: ustest_f16i32:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v0.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtun v0.2s, v1.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtun2 v0.4s, v2.2d
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x half> %x to <4 x i64>
|
|
%0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
|
|
%spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
|
|
%1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer
|
|
%spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer
|
|
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
|
|
ret <4 x i32> %conv6
|
|
}
|
|
|
|
; i16 saturate
|
|
|
|
define <2 x i16> @stest_f64i16(<2 x double> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f64i16:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-CVT-SD-NEXT: movi v1.2s, #127, msl #8
|
|
; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-CVT-SD-NEXT: mvni v1.2s, #127, msl #8
|
|
; CHECK-CVT-SD-NEXT: smax v0.2s, v0.2s, v1.2s
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f64i16:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-FP16-SD-NEXT: movi v1.2s, #127, msl #8
|
|
; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-FP16-SD-NEXT: mvni v1.2s, #127, msl #8
|
|
; CHECK-FP16-SD-NEXT: smax v0.2s, v0.2s, v1.2s
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f64i16:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-CVT-GI-NEXT: movi v1.2s, #127, msl #8
|
|
; CHECK-CVT-GI-NEXT: mvni v2.2s, #127, msl #8
|
|
; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-CVT-GI-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-CVT-GI-NEXT: smax v0.2s, v0.2s, v2.2s
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f64i16:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-FP16-GI-NEXT: movi v1.2s, #127, msl #8
|
|
; CHECK-FP16-GI-NEXT: mvni v2.2s, #127, msl #8
|
|
; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-FP16-GI-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-FP16-GI-NEXT: smax v0.2s, v0.2s, v2.2s
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i32>
|
|
%0 = icmp slt <2 x i32> %conv, <i32 32767, i32 32767>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>
|
|
%1 = icmp sgt <2 x i32> %spec.store.select, <i32 -32768, i32 -32768>
|
|
%spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768>
|
|
%conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
|
|
ret <2 x i16> %conv6
|
|
}
|
|
|
|
define <2 x i16> @utest_f64i16(<2 x double> %x) {
|
|
; CHECK-LABEL: utest_f64i16:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu v0.2d, v0.2d
|
|
; CHECK-NEXT: movi d1, #0x00ffff0000ffff
|
|
; CHECK-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <2 x double> %x to <2 x i32>
|
|
%0 = icmp ult <2 x i32> %conv, <i32 65535, i32 65535>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>
|
|
%conv6 = trunc <2 x i32> %spec.store.select to <2 x i16>
|
|
ret <2 x i16> %conv6
|
|
}
|
|
|
|
define <2 x i16> @ustest_f64i16(<2 x double> %x) {
|
|
; CHECK-LABEL: ustest_f64i16:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-NEXT: movi d1, #0x00ffff0000ffff
|
|
; CHECK-NEXT: movi v2.2d, #0000000000000000
|
|
; CHECK-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-NEXT: smax v0.2s, v0.2s, v2.2s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i32>
|
|
%0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>
|
|
%1 = icmp sgt <2 x i32> %spec.store.select, zeroinitializer
|
|
%spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> zeroinitializer
|
|
%conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
|
|
ret <2 x i16> %conv6
|
|
}
|
|
|
|
define <4 x i16> @stest_f32i16(<4 x float> %x) {
|
|
; CHECK-LABEL: stest_f32i16:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-NEXT: sqxtn v0.4h, v0.4s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x float> %x to <4 x i32>
|
|
%0 = icmp slt <4 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767>
|
|
%spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
|
|
%1 = icmp sgt <4 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
|
|
%spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
|
|
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
|
|
ret <4 x i16> %conv6
|
|
}
|
|
|
|
define <4 x i16> @utest_f32i16(<4 x float> %x) {
|
|
; CHECK-LABEL: utest_f32i16:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu v0.4s, v0.4s
|
|
; CHECK-NEXT: uqxtn v0.4h, v0.4s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <4 x float> %x to <4 x i32>
|
|
%0 = icmp ult <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>
|
|
%spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
|
|
%conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>
|
|
ret <4 x i16> %conv6
|
|
}
|
|
|
|
define <4 x i16> @ustest_f32i16(<4 x float> %x) {
|
|
; CHECK-LABEL: ustest_f32i16:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-NEXT: sqxtun v0.4h, v0.4s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x float> %x to <4 x i32>
|
|
%0 = icmp slt <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>
|
|
%spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
|
|
%1 = icmp sgt <4 x i32> %spec.store.select, zeroinitializer
|
|
%spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> zeroinitializer
|
|
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
|
|
ret <4 x i16> %conv6
|
|
}
|
|
|
|
define <8 x i16> @stest_f16i16(<8 x half> %x) {
|
|
; CHECK-CVT-LABEL: stest_f16i16:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
|
|
; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
|
|
; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
|
|
; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f16i16:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f16i16:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v1.4s, v1.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v0.4s
|
|
; CHECK-FP16-GI-NEXT: sqxtn v0.4h, v1.4s
|
|
; CHECK-FP16-GI-NEXT: sqxtn2 v0.8h, v2.4s
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <8 x half> %x to <8 x i32>
|
|
%0 = icmp slt <8 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
|
|
%spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
|
|
%1 = icmp sgt <8 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>
|
|
%spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>
|
|
%conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
|
|
ret <8 x i16> %conv6
|
|
}
|
|
|
|
define <8 x i16> @utest_f16i16(<8 x half> %x) {
|
|
; CHECK-CVT-LABEL: utest_f16i16:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
|
|
; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
|
|
; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
|
|
; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: utest_f16i16:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: utest_f16i16:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-FP16-GI-NEXT: fcvtzu v1.4s, v1.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzu v2.4s, v0.4s
|
|
; CHECK-FP16-GI-NEXT: uqxtn v0.4h, v1.4s
|
|
; CHECK-FP16-GI-NEXT: uqxtn2 v0.8h, v2.4s
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <8 x half> %x to <8 x i32>
|
|
%0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
|
|
%spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
|
|
%conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>
|
|
ret <8 x i16> %conv6
|
|
}
|
|
|
|
define <8 x i16> @ustest_f16i16(<8 x half> %x) {
|
|
; CHECK-CVT-LABEL: ustest_f16i16:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
|
|
; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
|
|
; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
|
|
; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f16i16:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f16i16:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v1.4s, v1.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v0.4s
|
|
; CHECK-FP16-GI-NEXT: sqxtun v0.4h, v1.4s
|
|
; CHECK-FP16-GI-NEXT: sqxtun2 v0.8h, v2.4s
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <8 x half> %x to <8 x i32>
|
|
%0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
|
|
%spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
|
|
%1 = icmp sgt <8 x i32> %spec.store.select, zeroinitializer
|
|
%spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> zeroinitializer
|
|
%conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
|
|
ret <8 x i16> %conv6
|
|
}
|
|
|
|
; i64 saturate
|
|
|
|
define <2 x i64> @stest_f64i64(<2 x double> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f64i64:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f64i64:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f64i64:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w21, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w22, -32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -40
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -48
|
|
; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-CVT-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-CVT-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixdfti
|
|
; CHECK-CVT-GI-NEXT: fmov d0, d8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixdfti
|
|
; CHECK-CVT-GI-NEXT: cmp x19, x21
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #0
|
|
; CHECK-CVT-GI-NEXT: cset w9, mi
|
|
; CHECK-CVT-GI-NEXT: csel w8, w8, w9, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x0, x21
|
|
; CHECK-CVT-GI-NEXT: cset w9, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, mi
|
|
; CHECK-CVT-GI-NEXT: csel w9, w9, w10, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, x21, ne
|
|
; CHECK-CVT-GI-NEXT: csel x10, x20, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, x21, ne
|
|
; CHECK-CVT-GI-NEXT: csel x11, x1, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, x22
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x10, #1
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, x22
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x11, #1
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, x22, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, x22, ne
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f64i64:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w21, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w22, -32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -40
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -48
|
|
; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-FP16-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-FP16-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixdfti
|
|
; CHECK-FP16-GI-NEXT: fmov d0, d8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixdfti
|
|
; CHECK-FP16-GI-NEXT: cmp x19, x21
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #0
|
|
; CHECK-FP16-GI-NEXT: cset w9, mi
|
|
; CHECK-FP16-GI-NEXT: csel w8, w8, w9, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x0, x21
|
|
; CHECK-FP16-GI-NEXT: cset w9, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, mi
|
|
; CHECK-FP16-GI-NEXT: csel w9, w9, w10, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, x21, ne
|
|
; CHECK-FP16-GI-NEXT: csel x10, x20, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, x21, ne
|
|
; CHECK-FP16-GI-NEXT: csel x11, x1, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, x22
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x10, #1
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, x22
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x11, #1
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, x22, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, x22, ne
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i128>
|
|
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>
|
|
%1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>
|
|
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @utest_f64i64(<2 x double> %x) {
|
|
; CHECK-CVT-SD-LABEL: utest_f64i64:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixunsdfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixunsdfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #0
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #0
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x8
|
|
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: utest_f64i64:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixunsdfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixunsdfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #0
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #0
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x8
|
|
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: utest_f64i64:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixunsdfti
|
|
; CHECK-CVT-GI-NEXT: fmov d0, d8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixunsdfti
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #1
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lo
|
|
; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #1
|
|
; CHECK-CVT-GI-NEXT: cset w9, lo
|
|
; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: utest_f64i64:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixunsdfti
|
|
; CHECK-FP16-GI-NEXT: fmov d0, d8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixunsdfti
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #1
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lo
|
|
; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #1
|
|
; CHECK-FP16-GI-NEXT: cset w9, lo
|
|
; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <2 x double> %x to <2 x i128>
|
|
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
|
|
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @ustest_f64i64(<2 x double> %x) {
|
|
; CHECK-CVT-SD-LABEL: ustest_f64i64:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixdfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixdfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #1
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #1
|
|
; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp xzr, x10
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: ngcs xzr, x11
|
|
; CHECK-CVT-SD-NEXT: csel x10, x10, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp xzr, x8
|
|
; CHECK-CVT-SD-NEXT: ngcs xzr, x9
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x10
|
|
; CHECK-CVT-SD-NEXT: csel x8, x8, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f64i64:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixdfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixdfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #1
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #1
|
|
; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp xzr, x10
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: ngcs xzr, x11
|
|
; CHECK-FP16-SD-NEXT: csel x10, x10, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp xzr, x8
|
|
; CHECK-FP16-SD-NEXT: ngcs xzr, x9
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x10
|
|
; CHECK-FP16-SD-NEXT: csel x8, x8, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: ustest_f64i64:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixdfti
|
|
; CHECK-CVT-GI-NEXT: fmov d0, d8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixdfti
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #1
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lt
|
|
; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #1
|
|
; CHECK-CVT-GI-NEXT: cset w9, lt
|
|
; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x10, x20, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x11, x1, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, gt
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w11, gt
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f64i64:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixdfti
|
|
; CHECK-FP16-GI-NEXT: fmov d0, d8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixdfti
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #1
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lt
|
|
; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #1
|
|
; CHECK-FP16-GI-NEXT: cset w9, lt
|
|
; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x10, x20, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x11, x1, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, gt
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w11, gt
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i128>
|
|
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
|
|
%1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer
|
|
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @stest_f32i64(<2 x float> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f32i64:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtl v0.2d, v0.2s
|
|
; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f32i64:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtl v0.2d, v0.2s
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f32i64:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w21, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w22, -32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -40
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -48
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-CVT-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-CVT-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixsfti
|
|
; CHECK-CVT-GI-NEXT: fmov s0, s8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixsfti
|
|
; CHECK-CVT-GI-NEXT: cmp x19, x21
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #0
|
|
; CHECK-CVT-GI-NEXT: cset w9, mi
|
|
; CHECK-CVT-GI-NEXT: csel w8, w8, w9, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x0, x21
|
|
; CHECK-CVT-GI-NEXT: cset w9, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, mi
|
|
; CHECK-CVT-GI-NEXT: csel w9, w9, w10, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, x21, ne
|
|
; CHECK-CVT-GI-NEXT: csel x10, x20, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, x21, ne
|
|
; CHECK-CVT-GI-NEXT: csel x11, x1, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, x22
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x10, #1
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, x22
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x11, #1
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, x22, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, x22, ne
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f32i64:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w21, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w22, -32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -40
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -48
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-FP16-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-FP16-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixsfti
|
|
; CHECK-FP16-GI-NEXT: fmov s0, s8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixsfti
|
|
; CHECK-FP16-GI-NEXT: cmp x19, x21
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #0
|
|
; CHECK-FP16-GI-NEXT: cset w9, mi
|
|
; CHECK-FP16-GI-NEXT: csel w8, w8, w9, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x0, x21
|
|
; CHECK-FP16-GI-NEXT: cset w9, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, mi
|
|
; CHECK-FP16-GI-NEXT: csel w9, w9, w10, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, x21, ne
|
|
; CHECK-FP16-GI-NEXT: csel x10, x20, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, x21, ne
|
|
; CHECK-FP16-GI-NEXT: csel x11, x1, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, x22
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x10, #1
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, x22
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x11, #1
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, x22, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, x22, ne
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x float> %x to <2 x i128>
|
|
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>
|
|
%1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>
|
|
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @utest_f32i64(<2 x float> %x) {
|
|
; CHECK-CVT-SD-LABEL: utest_f32i64:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixunssfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixunssfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #0
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #0
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x8
|
|
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: utest_f32i64:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixunssfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixunssfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #0
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #0
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x8
|
|
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: utest_f32i64:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixunssfti
|
|
; CHECK-CVT-GI-NEXT: fmov s0, s8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixunssfti
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #1
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lo
|
|
; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #1
|
|
; CHECK-CVT-GI-NEXT: cset w9, lo
|
|
; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: utest_f32i64:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixunssfti
|
|
; CHECK-FP16-GI-NEXT: fmov s0, s8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixunssfti
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #1
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lo
|
|
; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #1
|
|
; CHECK-FP16-GI-NEXT: cset w9, lo
|
|
; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <2 x float> %x to <2 x i128>
|
|
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
|
|
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @ustest_f32i64(<2 x float> %x) {
|
|
; CHECK-CVT-SD-LABEL: ustest_f32i64:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixsfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixsfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #1
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csinc x8, x1, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csel x9, x0, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #1
|
|
; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp xzr, x10
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: ngcs xzr, x11
|
|
; CHECK-CVT-SD-NEXT: csel x10, x10, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp xzr, x9
|
|
; CHECK-CVT-SD-NEXT: ngcs xzr, x8
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x10
|
|
; CHECK-CVT-SD-NEXT: csel x8, x9, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f32i64:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixsfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixsfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #1
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csinc x8, x1, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csel x9, x0, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #1
|
|
; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp xzr, x10
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: ngcs xzr, x11
|
|
; CHECK-FP16-SD-NEXT: csel x10, x10, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp xzr, x9
|
|
; CHECK-FP16-SD-NEXT: ngcs xzr, x8
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x10
|
|
; CHECK-FP16-SD-NEXT: csel x8, x9, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: ustest_f32i64:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixsfti
|
|
; CHECK-CVT-GI-NEXT: fmov s0, s8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixsfti
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #1
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lt
|
|
; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #1
|
|
; CHECK-CVT-GI-NEXT: cset w9, lt
|
|
; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x10, x20, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x11, x1, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, gt
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w11, gt
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f32i64:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixsfti
|
|
; CHECK-FP16-GI-NEXT: fmov s0, s8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixsfti
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #1
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lt
|
|
; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #1
|
|
; CHECK-FP16-GI-NEXT: cset w9, lt
|
|
; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x10, x20, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x11, x1, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, gt
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w11, gt
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x float> %x to <2 x i128>
|
|
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
|
|
%1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer
|
|
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @stest_f16i64(<2 x half> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f16i64:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: mov h1, v0.h[1]
|
|
; CHECK-CVT-SD-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-SD-NEXT: fcvt s1, h1
|
|
; CHECK-CVT-SD-NEXT: fcvtzs x8, s0
|
|
; CHECK-CVT-SD-NEXT: fcvtzs x9, s1
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x8
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f16i64:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: mov h1, v0.h[1]
|
|
; CHECK-FP16-SD-NEXT: fcvtzs x8, h0
|
|
; CHECK-FP16-SD-NEXT: fcvtzs x9, h1
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x8
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f16i64:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-CVT-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-CVT-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-CVT-GI-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-GI-NEXT: fcvt s1, h1
|
|
; CHECK-CVT-GI-NEXT: fcvtzs x9, s0
|
|
; CHECK-CVT-GI-NEXT: fcvtzs x10, s1
|
|
; CHECK-CVT-GI-NEXT: asr x11, x9, #63
|
|
; CHECK-CVT-GI-NEXT: cmp x9, x8
|
|
; CHECK-CVT-GI-NEXT: cset w12, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: asr x13, x10, #63
|
|
; CHECK-CVT-GI-NEXT: cset w14, mi
|
|
; CHECK-CVT-GI-NEXT: csel w12, w12, w14, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x10, x8
|
|
; CHECK-CVT-GI-NEXT: cset w14, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x13, #0
|
|
; CHECK-CVT-GI-NEXT: cset w15, mi
|
|
; CHECK-CVT-GI-NEXT: csel w14, w14, w15, eq
|
|
; CHECK-CVT-GI-NEXT: tst w12, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, x8, ne
|
|
; CHECK-CVT-GI-NEXT: csel x11, x11, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w14, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x10, x8, ne
|
|
; CHECK-CVT-GI-NEXT: csel x10, x13, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x9, x16
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x11, #1
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x8, x16
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x10, #1
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, x16, ne
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x9
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, x16, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x8
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f16i64:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-FP16-GI-NEXT: fcvtzs x9, h0
|
|
; CHECK-FP16-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-FP16-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-FP16-GI-NEXT: fcvtzs x10, h1
|
|
; CHECK-FP16-GI-NEXT: asr x11, x9, #63
|
|
; CHECK-FP16-GI-NEXT: cmp x9, x8
|
|
; CHECK-FP16-GI-NEXT: cset w12, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w14, mi
|
|
; CHECK-FP16-GI-NEXT: asr x13, x10, #63
|
|
; CHECK-FP16-GI-NEXT: csel w12, w12, w14, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x10, x8
|
|
; CHECK-FP16-GI-NEXT: cset w14, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x13, #0
|
|
; CHECK-FP16-GI-NEXT: cset w15, mi
|
|
; CHECK-FP16-GI-NEXT: csel w14, w14, w15, eq
|
|
; CHECK-FP16-GI-NEXT: tst w12, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, x8, ne
|
|
; CHECK-FP16-GI-NEXT: csel x11, x11, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w14, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x10, x8, ne
|
|
; CHECK-FP16-GI-NEXT: csel x10, x13, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x9, x16
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x11, #1
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x8, x16
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x10, #1
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, x16, ne
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x9
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, x16, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x8
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x half> %x to <2 x i128>
|
|
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>
|
|
%1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>
|
|
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @utest_f16i64(<2 x half> %x) {
|
|
; CHECK-CVT-SD-LABEL: utest_f16i64:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixunshfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixunshfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #0
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #0
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x8
|
|
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: utest_f16i64:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixunshfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixunshfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #0
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #0
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x8
|
|
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: utest_f16i64:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-CVT-GI-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-GI-NEXT: fcvt s1, h1
|
|
; CHECK-CVT-GI-NEXT: fcvtzu x8, s0
|
|
; CHECK-CVT-GI-NEXT: fcvtzu x9, s1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: utest_f16i64:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-FP16-GI-NEXT: fcvtzu x8, h0
|
|
; CHECK-FP16-GI-NEXT: fcvtzu x9, h1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <2 x half> %x to <2 x i128>
|
|
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
|
|
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @ustest_f16i64(<2 x half> %x) {
|
|
; CHECK-CVT-SD-LABEL: ustest_f16i64:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixhfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixhfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #1
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csinc x8, x1, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csel x9, x0, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #1
|
|
; CHECK-CVT-SD-NEXT: csel x10, x19, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csinc x11, x20, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp xzr, x10
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: ngcs xzr, x11
|
|
; CHECK-CVT-SD-NEXT: csel x10, x10, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp xzr, x9
|
|
; CHECK-CVT-SD-NEXT: ngcs xzr, x8
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x10
|
|
; CHECK-CVT-SD-NEXT: csel x8, x9, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f16i64:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixhfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixhfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #1
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csinc x8, x1, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csel x9, x0, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #1
|
|
; CHECK-FP16-SD-NEXT: csel x10, x19, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csinc x11, x20, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp xzr, x10
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: ngcs xzr, x11
|
|
; CHECK-FP16-SD-NEXT: csel x10, x10, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp xzr, x9
|
|
; CHECK-FP16-SD-NEXT: ngcs xzr, x8
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x10
|
|
; CHECK-FP16-SD-NEXT: csel x8, x9, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: ustest_f16i64:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-CVT-GI-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-GI-NEXT: fcvt s1, h1
|
|
; CHECK-CVT-GI-NEXT: fcvtzs x8, s0
|
|
; CHECK-CVT-GI-NEXT: fcvtzs x9, s1
|
|
; CHECK-CVT-GI-NEXT: asr x10, x8, #63
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #1
|
|
; CHECK-CVT-GI-NEXT: asr x11, x9, #63
|
|
; CHECK-CVT-GI-NEXT: cset w12, lt
|
|
; CHECK-CVT-GI-NEXT: csel w12, wzr, w12, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #1
|
|
; CHECK-CVT-GI-NEXT: cset w13, lt
|
|
; CHECK-CVT-GI-NEXT: csel w13, wzr, w13, eq
|
|
; CHECK-CVT-GI-NEXT: tst w12, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x10, x10, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w13, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x11, x11, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, gt
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w11, gt
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f16i64:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-FP16-GI-NEXT: fcvtzs x8, h0
|
|
; CHECK-FP16-GI-NEXT: fcvtzs x9, h1
|
|
; CHECK-FP16-GI-NEXT: asr x10, x8, #63
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #1
|
|
; CHECK-FP16-GI-NEXT: cset w12, lt
|
|
; CHECK-FP16-GI-NEXT: asr x11, x9, #63
|
|
; CHECK-FP16-GI-NEXT: csel w12, wzr, w12, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #1
|
|
; CHECK-FP16-GI-NEXT: cset w13, lt
|
|
; CHECK-FP16-GI-NEXT: csel w13, wzr, w13, eq
|
|
; CHECK-FP16-GI-NEXT: tst w12, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x10, x10, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w13, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x11, x11, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, gt
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w11, gt
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x half> %x to <2 x i128>
|
|
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
|
|
%spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>
|
|
%1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer
|
|
%spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
|
|
|
|
; i32 saturate
|
|
|
|
define <2 x i32> @stest_f64i32_mm(<2 x double> %x) {
|
|
; CHECK-LABEL: stest_f64i32_mm:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-NEXT: sqxtn v0.2s, v0.2d
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i64>
|
|
%spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>)
|
|
%spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>)
|
|
%conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
|
|
ret <2 x i32> %conv6
|
|
}
|
|
|
|
define <2 x i32> @utest_f64i32_mm(<2 x double> %x) {
|
|
; CHECK-CVT-SD-LABEL: utest_f64i32_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: mov d1, v0.d[1]
|
|
; CHECK-CVT-SD-NEXT: fcvtzu w8, d0
|
|
; CHECK-CVT-SD-NEXT: fcvtzu w9, d1
|
|
; CHECK-CVT-SD-NEXT: fmov s0, w8
|
|
; CHECK-CVT-SD-NEXT: mov v0.s[1], w9
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: utest_f64i32_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: mov d1, v0.d[1]
|
|
; CHECK-FP16-SD-NEXT: fcvtzu w8, d0
|
|
; CHECK-FP16-SD-NEXT: fcvtzu w9, d1
|
|
; CHECK-FP16-SD-NEXT: fmov s0, w8
|
|
; CHECK-FP16-SD-NEXT: mov v0.s[1], w9
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: utest_f64i32_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
|
|
; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
|
|
; CHECK-CVT-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
|
|
; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v2.16b
|
|
; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: utest_f64i32_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
|
|
; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
|
|
; CHECK-FP16-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
|
|
; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v2.16b
|
|
; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <2 x double> %x to <2 x i64>
|
|
%spec.store.select = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
|
|
%conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>
|
|
ret <2 x i32> %conv6
|
|
}
|
|
|
|
define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
|
|
; CHECK-LABEL: ustest_f64i32_mm:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-NEXT: sqxtun v0.2s, v0.2d
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i64>
|
|
%spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
|
|
%spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> zeroinitializer)
|
|
%conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>
|
|
ret <2 x i32> %conv6
|
|
}
|
|
|
|
define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f32i32_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f32i32_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f32i32_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
|
|
; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v0.2d
|
|
; CHECK-CVT-GI-NEXT: sqxtn v0.2s, v1.2d
|
|
; CHECK-CVT-GI-NEXT: sqxtn2 v0.4s, v2.2d
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f32i32_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v0.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtn v0.2s, v1.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtn2 v0.4s, v2.2d
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x float> %x to <4 x i64>
|
|
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
|
|
%spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)
|
|
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
|
|
ret <4 x i32> %conv6
|
|
}
|
|
|
|
define <4 x i32> @utest_f32i32_mm(<4 x float> %x) {
|
|
; CHECK-LABEL: utest_f32i32_mm:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu v0.4s, v0.4s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <4 x float> %x to <4 x i64>
|
|
%spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
|
|
%conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
|
|
ret <4 x i32> %conv6
|
|
}
|
|
|
|
define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
|
|
; CHECK-CVT-SD-LABEL: ustest_f32i32_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f32i32_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: ustest_f32i32_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
|
|
; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v0.2d
|
|
; CHECK-CVT-GI-NEXT: sqxtun v0.2s, v1.2d
|
|
; CHECK-CVT-GI-NEXT: sqxtun2 v0.4s, v2.2d
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f32i32_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v0.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtun v0.2s, v1.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtun2 v0.4s, v2.2d
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x float> %x to <4 x i64>
|
|
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
|
|
%spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)
|
|
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
|
|
ret <4 x i32> %conv6
|
|
}
|
|
|
|
define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f16i32_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f16i32_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f16i32_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
|
|
; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v0.2d
|
|
; CHECK-CVT-GI-NEXT: sqxtn v0.2s, v1.2d
|
|
; CHECK-CVT-GI-NEXT: sqxtn2 v0.4s, v2.2d
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f16i32_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v0.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtn v0.2s, v1.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtn2 v0.4s, v2.2d
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x half> %x to <4 x i64>
|
|
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
|
|
%spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)
|
|
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
|
|
ret <4 x i32> %conv6
|
|
}
|
|
|
|
define <4 x i32> @utest_f16i32_mm(<4 x half> %x) {
|
|
; CHECK-LABEL: utest_f16i32_mm:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-NEXT: fcvtzu v0.4s, v0.4s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <4 x half> %x to <4 x i64>
|
|
%spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
|
|
%conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>
|
|
ret <4 x i32> %conv6
|
|
}
|
|
|
|
define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
|
|
; CHECK-CVT-SD-LABEL: ustest_f16i32_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f16i32_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: ustest_f16i32_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
|
|
; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v0.2d
|
|
; CHECK-CVT-GI-NEXT: sqxtun v0.2s, v1.2d
|
|
; CHECK-CVT-GI-NEXT: sqxtun2 v0.4s, v2.2d
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f16i32_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.2d, v0.2s
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.2d, v0.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v1.2d
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v0.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtun v0.2s, v1.2d
|
|
; CHECK-FP16-GI-NEXT: sqxtun2 v0.4s, v2.2d
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x half> %x to <4 x i64>
|
|
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
|
|
%spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)
|
|
%conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>
|
|
ret <4 x i32> %conv6
|
|
}
|
|
|
|
; i16 saturate
|
|
|
|
define <2 x i16> @stest_f64i16_mm(<2 x double> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f64i16_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-CVT-SD-NEXT: movi v1.2s, #127, msl #8
|
|
; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-CVT-SD-NEXT: mvni v1.2s, #127, msl #8
|
|
; CHECK-CVT-SD-NEXT: smax v0.2s, v0.2s, v1.2s
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f64i16_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-FP16-SD-NEXT: movi v1.2s, #127, msl #8
|
|
; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-FP16-SD-NEXT: mvni v1.2s, #127, msl #8
|
|
; CHECK-FP16-SD-NEXT: smax v0.2s, v0.2s, v1.2s
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f64i16_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-CVT-GI-NEXT: movi v1.2s, #127, msl #8
|
|
; CHECK-CVT-GI-NEXT: mvni v2.2s, #127, msl #8
|
|
; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-CVT-GI-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-CVT-GI-NEXT: smax v0.2s, v0.2s, v2.2s
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f64i16_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-FP16-GI-NEXT: movi v1.2s, #127, msl #8
|
|
; CHECK-FP16-GI-NEXT: mvni v2.2s, #127, msl #8
|
|
; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-FP16-GI-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-FP16-GI-NEXT: smax v0.2s, v0.2s, v2.2s
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i32>
|
|
%spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>)
|
|
%spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768>)
|
|
%conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
|
|
ret <2 x i16> %conv6
|
|
}
|
|
|
|
define <2 x i16> @utest_f64i16_mm(<2 x double> %x) {
|
|
; CHECK-LABEL: utest_f64i16_mm:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu v0.2d, v0.2d
|
|
; CHECK-NEXT: movi d1, #0x00ffff0000ffff
|
|
; CHECK-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-NEXT: umin v0.2s, v0.2s, v1.2s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <2 x double> %x to <2 x i32>
|
|
%spec.store.select = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)
|
|
%conv6 = trunc <2 x i32> %spec.store.select to <2 x i16>
|
|
ret <2 x i16> %conv6
|
|
}
|
|
|
|
define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) {
|
|
; CHECK-LABEL: ustest_f64i16_mm:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-NEXT: movi d1, #0x00ffff0000ffff
|
|
; CHECK-NEXT: movi v2.2d, #0000000000000000
|
|
; CHECK-NEXT: xtn v0.2s, v0.2d
|
|
; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
|
|
; CHECK-NEXT: smax v0.2s, v0.2s, v2.2s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i32>
|
|
%spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)
|
|
%spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> zeroinitializer)
|
|
%conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>
|
|
ret <2 x i16> %conv6
|
|
}
|
|
|
|
define <4 x i16> @stest_f32i16_mm(<4 x float> %x) {
|
|
; CHECK-LABEL: stest_f32i16_mm:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-NEXT: sqxtn v0.4h, v0.4s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x float> %x to <4 x i32>
|
|
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
|
|
%spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
|
|
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
|
|
ret <4 x i16> %conv6
|
|
}
|
|
|
|
define <4 x i16> @utest_f32i16_mm(<4 x float> %x) {
|
|
; CHECK-LABEL: utest_f32i16_mm:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzu v0.4s, v0.4s
|
|
; CHECK-NEXT: uqxtn v0.4h, v0.4s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <4 x float> %x to <4 x i32>
|
|
%spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
|
|
%conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>
|
|
ret <4 x i16> %conv6
|
|
}
|
|
|
|
define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {
|
|
; CHECK-LABEL: ustest_f32i16_mm:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-NEXT: sqxtun v0.4h, v0.4s
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x float> %x to <4 x i32>
|
|
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
|
|
%spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)
|
|
%conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
|
|
ret <4 x i16> %conv6
|
|
}
|
|
|
|
define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
|
|
; CHECK-CVT-LABEL: stest_f16i16_mm:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
|
|
; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
|
|
; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
|
|
; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f16i16_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f16i16_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v1.4s, v1.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v0.4s
|
|
; CHECK-FP16-GI-NEXT: sqxtn v0.4h, v1.4s
|
|
; CHECK-FP16-GI-NEXT: sqxtn2 v0.8h, v2.4s
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <8 x half> %x to <8 x i32>
|
|
%spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
|
|
%spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
|
|
%conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
|
|
ret <8 x i16> %conv6
|
|
}
|
|
|
|
define <8 x i16> @utest_f16i16_mm(<8 x half> %x) {
|
|
; CHECK-CVT-LABEL: utest_f16i16_mm:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
|
|
; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
|
|
; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
|
|
; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: utest_f16i16_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: utest_f16i16_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-FP16-GI-NEXT: fcvtzu v1.4s, v1.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzu v2.4s, v0.4s
|
|
; CHECK-FP16-GI-NEXT: uqxtn v0.4h, v1.4s
|
|
; CHECK-FP16-GI-NEXT: uqxtn2 v0.8h, v2.4s
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <8 x half> %x to <8 x i32>
|
|
%spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
|
|
%conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>
|
|
ret <8 x i16> %conv6
|
|
}
|
|
|
|
define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
|
|
; CHECK-CVT-LABEL: ustest_f16i16_mm:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
|
|
; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
|
|
; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
|
|
; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f16i16_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f16i16_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v1.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: fcvtl2 v0.4s, v0.8h
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v1.4s, v1.4s
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v2.4s, v0.4s
|
|
; CHECK-FP16-GI-NEXT: sqxtun v0.4h, v1.4s
|
|
; CHECK-FP16-GI-NEXT: sqxtun2 v0.8h, v2.4s
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <8 x half> %x to <8 x i32>
|
|
%spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
|
|
%spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> zeroinitializer)
|
|
%conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>
|
|
ret <8 x i16> %conv6
|
|
}
|
|
|
|
; i64 saturate
|
|
|
|
define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f64i64_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f64i64_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f64i64_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w21, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w22, -32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -40
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -48
|
|
; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-CVT-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-CVT-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixdfti
|
|
; CHECK-CVT-GI-NEXT: fmov d0, d8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixdfti
|
|
; CHECK-CVT-GI-NEXT: cmp x19, x21
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #0
|
|
; CHECK-CVT-GI-NEXT: cset w9, mi
|
|
; CHECK-CVT-GI-NEXT: csel w8, w8, w9, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x0, x21
|
|
; CHECK-CVT-GI-NEXT: cset w9, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, mi
|
|
; CHECK-CVT-GI-NEXT: csel w9, w9, w10, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, x21, ne
|
|
; CHECK-CVT-GI-NEXT: csel x10, x20, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, x21, ne
|
|
; CHECK-CVT-GI-NEXT: csel x11, x1, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, x22
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x10, #1
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, x22
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x11, #1
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, x22, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, x22, ne
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f64i64_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w21, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w22, -32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -40
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -48
|
|
; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-FP16-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-FP16-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixdfti
|
|
; CHECK-FP16-GI-NEXT: fmov d0, d8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixdfti
|
|
; CHECK-FP16-GI-NEXT: cmp x19, x21
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #0
|
|
; CHECK-FP16-GI-NEXT: cset w9, mi
|
|
; CHECK-FP16-GI-NEXT: csel w8, w8, w9, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x0, x21
|
|
; CHECK-FP16-GI-NEXT: cset w9, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, mi
|
|
; CHECK-FP16-GI-NEXT: csel w9, w9, w10, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, x21, ne
|
|
; CHECK-FP16-GI-NEXT: csel x10, x20, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, x21, ne
|
|
; CHECK-FP16-GI-NEXT: csel x11, x1, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, x22
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x10, #1
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, x22
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x11, #1
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, x22, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, x22, ne
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i128>
|
|
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
|
|
%spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @utest_f64i64_mm(<2 x double> %x) {
|
|
; CHECK-CVT-SD-LABEL: utest_f64i64_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixunsdfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixunsdfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #0
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #0
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x8
|
|
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: utest_f64i64_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixunsdfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixunsdfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #0
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #0
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x8
|
|
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: utest_f64i64_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixunsdfti
|
|
; CHECK-CVT-GI-NEXT: fmov d0, d8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixunsdfti
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #1
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lo
|
|
; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #1
|
|
; CHECK-CVT-GI-NEXT: cset w9, lo
|
|
; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: utest_f64i64_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixunsdfti
|
|
; CHECK-FP16-GI-NEXT: fmov d0, d8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixunsdfti
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #1
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lo
|
|
; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #1
|
|
; CHECK-FP16-GI-NEXT: cset w9, lo
|
|
; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <2 x double> %x to <2 x i128>
|
|
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
|
|
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
|
|
; CHECK-CVT-SD-LABEL: ustest_f64i64_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixdfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixdfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #1
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #1
|
|
; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp x10, #0
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
|
|
; CHECK-CVT-SD-NEXT: cmp x9, #0
|
|
; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x10
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f64i64_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixdfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixdfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #1
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #1
|
|
; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp x10, #0
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
|
|
; CHECK-FP16-SD-NEXT: cmp x9, #0
|
|
; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x10
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: ustest_f64i64_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-CVT-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixdfti
|
|
; CHECK-CVT-GI-NEXT: fmov d0, d8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixdfti
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #1
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lt
|
|
; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #1
|
|
; CHECK-CVT-GI-NEXT: cset w9, lt
|
|
; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x10, x20, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x11, x1, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, gt
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w11, gt
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f64i64_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-FP16-GI-NEXT: mov d8, v0.d[1]
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixdfti
|
|
; CHECK-FP16-GI-NEXT: fmov d0, d8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixdfti
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #1
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lt
|
|
; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #1
|
|
; CHECK-FP16-GI-NEXT: cset w9, lt
|
|
; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x10, x20, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x11, x1, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, gt
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w11, gt
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x double> %x to <2 x i128>
|
|
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
|
|
%spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f32i64_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtl v0.2d, v0.2s
|
|
; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f32i64_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtl v0.2d, v0.2s
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f32i64_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w21, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w22, -32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -40
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -48
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-CVT-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-CVT-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixsfti
|
|
; CHECK-CVT-GI-NEXT: fmov s0, s8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixsfti
|
|
; CHECK-CVT-GI-NEXT: cmp x19, x21
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #0
|
|
; CHECK-CVT-GI-NEXT: cset w9, mi
|
|
; CHECK-CVT-GI-NEXT: csel w8, w8, w9, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x0, x21
|
|
; CHECK-CVT-GI-NEXT: cset w9, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, mi
|
|
; CHECK-CVT-GI-NEXT: csel w9, w9, w10, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, x21, ne
|
|
; CHECK-CVT-GI-NEXT: csel x10, x20, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, x21, ne
|
|
; CHECK-CVT-GI-NEXT: csel x11, x1, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, x22
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x10, #1
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, x22
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x11, #1
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, x22, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, x22, ne
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f32i64_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w21, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w22, -32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -40
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -48
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-FP16-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-FP16-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixsfti
|
|
; CHECK-FP16-GI-NEXT: fmov s0, s8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixsfti
|
|
; CHECK-FP16-GI-NEXT: cmp x19, x21
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #0
|
|
; CHECK-FP16-GI-NEXT: cset w9, mi
|
|
; CHECK-FP16-GI-NEXT: csel w8, w8, w9, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x0, x21
|
|
; CHECK-FP16-GI-NEXT: cset w9, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, mi
|
|
; CHECK-FP16-GI-NEXT: csel w9, w9, w10, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, x21, ne
|
|
; CHECK-FP16-GI-NEXT: csel x10, x20, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, x21, ne
|
|
; CHECK-FP16-GI-NEXT: csel x11, x1, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, x22
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x10, #1
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, x22
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x11, #1
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, x22, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, x22, ne
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x float> %x to <2 x i128>
|
|
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
|
|
%spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @utest_f32i64_mm(<2 x float> %x) {
|
|
; CHECK-CVT-SD-LABEL: utest_f32i64_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixunssfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixunssfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #0
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #0
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x8
|
|
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: utest_f32i64_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixunssfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixunssfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #0
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #0
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x8
|
|
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: utest_f32i64_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixunssfti
|
|
; CHECK-CVT-GI-NEXT: fmov s0, s8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixunssfti
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #1
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lo
|
|
; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #1
|
|
; CHECK-CVT-GI-NEXT: cset w9, lo
|
|
; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: utest_f32i64_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixunssfti
|
|
; CHECK-FP16-GI-NEXT: fmov s0, s8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixunssfti
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #1
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lo
|
|
; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #1
|
|
; CHECK-FP16-GI-NEXT: cset w9, lo
|
|
; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <2 x float> %x to <2 x i128>
|
|
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
|
|
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
|
|
; CHECK-CVT-SD-LABEL: ustest_f32i64_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixsfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixsfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #1
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #1
|
|
; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp x10, #0
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
|
|
; CHECK-CVT-SD-NEXT: cmp x9, #0
|
|
; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x10
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f32i64_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixsfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixsfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #1
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #1
|
|
; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp x10, #0
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
|
|
; CHECK-FP16-SD-NEXT: cmp x9, #0
|
|
; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x10
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: ustest_f32i64_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-CVT-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-CVT-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-CVT-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-CVT-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-CVT-GI-NEXT: bl __fixsfti
|
|
; CHECK-CVT-GI-NEXT: fmov s0, s8
|
|
; CHECK-CVT-GI-NEXT: mov x19, x0
|
|
; CHECK-CVT-GI-NEXT: mov x20, x1
|
|
; CHECK-CVT-GI-NEXT: bl __fixsfti
|
|
; CHECK-CVT-GI-NEXT: cmp x20, #1
|
|
; CHECK-CVT-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-CVT-GI-NEXT: cset w8, lt
|
|
; CHECK-CVT-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x1, #1
|
|
; CHECK-CVT-GI-NEXT: cset w9, lt
|
|
; CHECK-CVT-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-CVT-GI-NEXT: tst w8, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x10, x20, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w9, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x11, x1, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, gt
|
|
; CHECK-CVT-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w11, gt
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f32i64_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: str x30, [sp, #8] // 8-byte Spill
|
|
; CHECK-FP16-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
|
|
; CHECK-FP16-GI-NEXT: .cfi_def_cfa_offset 32
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset w30, -24
|
|
; CHECK-FP16-GI-NEXT: .cfi_offset b8, -32
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov s8, v0.s[1]
|
|
; CHECK-FP16-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
|
|
; CHECK-FP16-GI-NEXT: bl __fixsfti
|
|
; CHECK-FP16-GI-NEXT: fmov s0, s8
|
|
; CHECK-FP16-GI-NEXT: mov x19, x0
|
|
; CHECK-FP16-GI-NEXT: mov x20, x1
|
|
; CHECK-FP16-GI-NEXT: bl __fixsfti
|
|
; CHECK-FP16-GI-NEXT: cmp x20, #1
|
|
; CHECK-FP16-GI-NEXT: ldr x30, [sp, #8] // 8-byte Reload
|
|
; CHECK-FP16-GI-NEXT: cset w8, lt
|
|
; CHECK-FP16-GI-NEXT: csel w8, wzr, w8, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x1, #1
|
|
; CHECK-FP16-GI-NEXT: cset w9, lt
|
|
; CHECK-FP16-GI-NEXT: csel w9, wzr, w9, eq
|
|
; CHECK-FP16-GI-NEXT: tst w8, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x19, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x10, x20, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w9, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x0, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x11, x1, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, gt
|
|
; CHECK-FP16-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w11, gt
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x float> %x to <2 x i128>
|
|
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
|
|
%spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
|
|
; CHECK-CVT-SD-LABEL: stest_f16i64_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: mov h1, v0.h[1]
|
|
; CHECK-CVT-SD-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-SD-NEXT: fcvt s1, h1
|
|
; CHECK-CVT-SD-NEXT: fcvtzs x8, s0
|
|
; CHECK-CVT-SD-NEXT: fcvtzs x9, s1
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x8
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: stest_f16i64_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: mov h1, v0.h[1]
|
|
; CHECK-FP16-SD-NEXT: fcvtzs x8, h0
|
|
; CHECK-FP16-SD-NEXT: fcvtzs x9, h1
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x8
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: stest_f16i64_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-CVT-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-CVT-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-CVT-GI-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-GI-NEXT: fcvt s1, h1
|
|
; CHECK-CVT-GI-NEXT: fcvtzs x9, s0
|
|
; CHECK-CVT-GI-NEXT: fcvtzs x10, s1
|
|
; CHECK-CVT-GI-NEXT: asr x11, x9, #63
|
|
; CHECK-CVT-GI-NEXT: cmp x9, x8
|
|
; CHECK-CVT-GI-NEXT: cset w12, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: asr x13, x10, #63
|
|
; CHECK-CVT-GI-NEXT: cset w14, mi
|
|
; CHECK-CVT-GI-NEXT: csel w12, w12, w14, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x10, x8
|
|
; CHECK-CVT-GI-NEXT: cset w14, lo
|
|
; CHECK-CVT-GI-NEXT: cmp x13, #0
|
|
; CHECK-CVT-GI-NEXT: cset w15, mi
|
|
; CHECK-CVT-GI-NEXT: csel w14, w14, w15, eq
|
|
; CHECK-CVT-GI-NEXT: tst w12, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, x8, ne
|
|
; CHECK-CVT-GI-NEXT: csel x11, x11, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w14, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x10, x8, ne
|
|
; CHECK-CVT-GI-NEXT: csel x10, x13, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x9, x16
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x11, #1
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x8, x16
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w13, pl
|
|
; CHECK-CVT-GI-NEXT: cmn x10, #1
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, x16, ne
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x9
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, x16, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x8
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: stest_f16i64_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-FP16-GI-NEXT: fcvtzs x9, h0
|
|
; CHECK-FP16-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
|
|
; CHECK-FP16-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
|
|
; CHECK-FP16-GI-NEXT: fcvtzs x10, h1
|
|
; CHECK-FP16-GI-NEXT: asr x11, x9, #63
|
|
; CHECK-FP16-GI-NEXT: cmp x9, x8
|
|
; CHECK-FP16-GI-NEXT: cset w12, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w14, mi
|
|
; CHECK-FP16-GI-NEXT: asr x13, x10, #63
|
|
; CHECK-FP16-GI-NEXT: csel w12, w12, w14, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x10, x8
|
|
; CHECK-FP16-GI-NEXT: cset w14, lo
|
|
; CHECK-FP16-GI-NEXT: cmp x13, #0
|
|
; CHECK-FP16-GI-NEXT: cset w15, mi
|
|
; CHECK-FP16-GI-NEXT: csel w14, w14, w15, eq
|
|
; CHECK-FP16-GI-NEXT: tst w12, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, x8, ne
|
|
; CHECK-FP16-GI-NEXT: csel x11, x11, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w14, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x10, x8, ne
|
|
; CHECK-FP16-GI-NEXT: csel x10, x13, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x9, x16
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x11, #1
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x8, x16
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w13, pl
|
|
; CHECK-FP16-GI-NEXT: cmn x10, #1
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, x16, ne
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x9
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, x16, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x8
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x half> %x to <2 x i128>
|
|
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
|
|
%spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @utest_f16i64_mm(<2 x half> %x) {
|
|
; CHECK-CVT-SD-LABEL: utest_f16i64_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixunshfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixunshfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #0
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #0
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x8
|
|
; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: utest_f16i64_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixunshfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixunshfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #0
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #0
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x8
|
|
; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: utest_f16i64_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-CVT-GI-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-GI-NEXT: fcvt s1, h1
|
|
; CHECK-CVT-GI-NEXT: fcvtzu x8, s0
|
|
; CHECK-CVT-GI-NEXT: fcvtzu x9, s1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: utest_f16i64_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-FP16-GI-NEXT: fcvtzu x8, h0
|
|
; CHECK-FP16-GI-NEXT: fcvtzu x9, h1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptoui <2 x half> %x to <2 x i128>
|
|
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
|
|
%conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {
|
|
; CHECK-CVT-SD-LABEL: ustest_f16i64_mm:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
|
|
; CHECK-CVT-SD-NEXT: bl __fixhfti
|
|
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-CVT-SD-NEXT: mov x19, x0
|
|
; CHECK-CVT-SD-NEXT: mov x20, x1
|
|
; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
|
|
; CHECK-CVT-SD-NEXT: bl __fixhfti
|
|
; CHECK-CVT-SD-NEXT: cmp x1, #1
|
|
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp x20, #1
|
|
; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
|
|
; CHECK-CVT-SD-NEXT: cmp x10, #0
|
|
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
|
|
; CHECK-CVT-SD-NEXT: cmp x9, #0
|
|
; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
|
|
; CHECK-CVT-SD-NEXT: fmov d0, x10
|
|
; CHECK-CVT-SD-NEXT: fmov d1, x8
|
|
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-CVT-SD-NEXT: add sp, sp, #48
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f16i64_mm:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: sub sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
|
|
; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
|
|
; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
|
|
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
|
|
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
|
|
; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
|
|
; CHECK-FP16-SD-NEXT: bl __fixhfti
|
|
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
|
|
; CHECK-FP16-SD-NEXT: mov x19, x0
|
|
; CHECK-FP16-SD-NEXT: mov x20, x1
|
|
; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
|
|
; CHECK-FP16-SD-NEXT: bl __fixhfti
|
|
; CHECK-FP16-SD-NEXT: cmp x1, #1
|
|
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
|
|
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp x20, #1
|
|
; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
|
|
; CHECK-FP16-SD-NEXT: cmp x10, #0
|
|
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
|
|
; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
|
|
; CHECK-FP16-SD-NEXT: cmp x9, #0
|
|
; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
|
|
; CHECK-FP16-SD-NEXT: fmov d0, x10
|
|
; CHECK-FP16-SD-NEXT: fmov d1, x8
|
|
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
|
|
; CHECK-FP16-SD-NEXT: add sp, sp, #48
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: ustest_f16i64_mm:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-CVT-GI-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-GI-NEXT: fcvt s1, h1
|
|
; CHECK-CVT-GI-NEXT: fcvtzs x8, s0
|
|
; CHECK-CVT-GI-NEXT: fcvtzs x9, s1
|
|
; CHECK-CVT-GI-NEXT: asr x10, x8, #63
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #1
|
|
; CHECK-CVT-GI-NEXT: asr x11, x9, #63
|
|
; CHECK-CVT-GI-NEXT: cset w12, lt
|
|
; CHECK-CVT-GI-NEXT: csel w12, wzr, w12, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #1
|
|
; CHECK-CVT-GI-NEXT: cset w13, lt
|
|
; CHECK-CVT-GI-NEXT: csel w13, wzr, w13, eq
|
|
; CHECK-CVT-GI-NEXT: tst w12, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x10, x10, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w13, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: csinc x11, x11, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: cmp x8, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x10, #0
|
|
; CHECK-CVT-GI-NEXT: cset w10, gt
|
|
; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-CVT-GI-NEXT: cmp x9, #0
|
|
; CHECK-CVT-GI-NEXT: cset w12, hi
|
|
; CHECK-CVT-GI-NEXT: cmp x11, #0
|
|
; CHECK-CVT-GI-NEXT: cset w11, gt
|
|
; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-CVT-GI-NEXT: tst w10, #0x1
|
|
; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: tst w11, #0x1
|
|
; CHECK-CVT-GI-NEXT: fmov d0, x8
|
|
; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f16i64_mm:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
|
|
; CHECK-FP16-GI-NEXT: fcvtzs x8, h0
|
|
; CHECK-FP16-GI-NEXT: fcvtzs x9, h1
|
|
; CHECK-FP16-GI-NEXT: asr x10, x8, #63
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #1
|
|
; CHECK-FP16-GI-NEXT: cset w12, lt
|
|
; CHECK-FP16-GI-NEXT: asr x11, x9, #63
|
|
; CHECK-FP16-GI-NEXT: csel w12, wzr, w12, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #1
|
|
; CHECK-FP16-GI-NEXT: cset w13, lt
|
|
; CHECK-FP16-GI-NEXT: csel w13, wzr, w13, eq
|
|
; CHECK-FP16-GI-NEXT: tst w12, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x10, x10, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w13, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: csinc x11, x11, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: cmp x8, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x10, #0
|
|
; CHECK-FP16-GI-NEXT: cset w10, gt
|
|
; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
|
|
; CHECK-FP16-GI-NEXT: cmp x9, #0
|
|
; CHECK-FP16-GI-NEXT: cset w12, hi
|
|
; CHECK-FP16-GI-NEXT: cmp x11, #0
|
|
; CHECK-FP16-GI-NEXT: cset w11, gt
|
|
; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
|
|
; CHECK-FP16-GI-NEXT: tst w10, #0x1
|
|
; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: tst w11, #0x1
|
|
; CHECK-FP16-GI-NEXT: fmov d0, x8
|
|
; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
|
|
; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <2 x half> %x to <2 x i128>
|
|
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
|
|
%spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)
|
|
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
|
|
ret <2 x i64> %conv6
|
|
}
|
|
|
|
; i32 non saturate
|
|
|
|
define <4 x i32> @ustest_f16i32_nsat(<4 x half> %x) {
|
|
; CHECK-CVT-SD-LABEL: ustest_f16i32_nsat:
|
|
; CHECK-CVT-SD: // %bb.0: // %entry
|
|
; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-CVT-SD-NEXT: movi v1.2d, #0000000000000000
|
|
; CHECK-CVT-SD-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-CVT-SD-NEXT: smin v0.4s, v0.4s, v1.4s
|
|
; CHECK-CVT-SD-NEXT: smax v0.4s, v0.4s, v1.4s
|
|
; CHECK-CVT-SD-NEXT: ret
|
|
;
|
|
; CHECK-FP16-SD-LABEL: ustest_f16i32_nsat:
|
|
; CHECK-FP16-SD: // %bb.0: // %entry
|
|
; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-FP16-SD-NEXT: movi v1.2d, #0000000000000000
|
|
; CHECK-FP16-SD-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-FP16-SD-NEXT: smin v0.4s, v0.4s, v1.4s
|
|
; CHECK-FP16-SD-NEXT: smax v0.4s, v0.4s, v1.4s
|
|
; CHECK-FP16-SD-NEXT: ret
|
|
;
|
|
; CHECK-CVT-GI-LABEL: ustest_f16i32_nsat:
|
|
; CHECK-CVT-GI: // %bb.0: // %entry
|
|
; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-CVT-GI-NEXT: movi v1.2d, #0000000000000000
|
|
; CHECK-CVT-GI-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-CVT-GI-NEXT: smin v0.4s, v1.4s, v0.4s
|
|
; CHECK-CVT-GI-NEXT: smax v0.4s, v0.4s, v1.4s
|
|
; CHECK-CVT-GI-NEXT: ret
|
|
;
|
|
; CHECK-FP16-GI-LABEL: ustest_f16i32_nsat:
|
|
; CHECK-FP16-GI: // %bb.0: // %entry
|
|
; CHECK-FP16-GI-NEXT: fcvtl v0.4s, v0.4h
|
|
; CHECK-FP16-GI-NEXT: movi v1.2d, #0000000000000000
|
|
; CHECK-FP16-GI-NEXT: fcvtzs v0.4s, v0.4s
|
|
; CHECK-FP16-GI-NEXT: smin v0.4s, v1.4s, v0.4s
|
|
; CHECK-FP16-GI-NEXT: smax v0.4s, v0.4s, v1.4s
|
|
; CHECK-FP16-GI-NEXT: ret
|
|
entry:
|
|
%conv = fptosi <4 x half> %x to <4 x i32>
|
|
%spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> zeroinitializer, <4 x i32> %conv)
|
|
%spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)
|
|
ret <4 x i32> %spec.store.select7
|
|
}
|
|
|
|
declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>)
|
|
declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>)
|
|
declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)
|
|
declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
|
|
declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
|
|
declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
|
|
declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)
|
|
declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)
|
|
declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)
|
|
declare <2 x i64> @llvm.smin.v2i64(<2 x i64>, <2 x i64>)
|
|
declare <2 x i64> @llvm.smax.v2i64(<2 x i64>, <2 x i64>)
|
|
declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)
|
|
declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)
|
|
declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)
|
|
declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)
|
|
declare <2 x i128> @llvm.smin.v2i128(<2 x i128>, <2 x i128>)
|
|
declare <2 x i128> @llvm.smax.v2i128(<2 x i128>, <2 x i128>)
|
|
declare <2 x i128> @llvm.umin.v2i128(<2 x i128>, <2 x i128>)
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
|
; CHECK-FP16: {{.*}}
|