TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/freeze-load-zext-copytoreg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin < %s | FileCheck %s

define i32 @freeze_i8_load_multi_bb(ptr %p, i64 %len) {
; CHECK-LABEL: freeze_i8_load_multi_bb:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    mov x8, xzr
; CHECK-NEXT:    b LBB0_2
; CHECK-NEXT:  LBB0_1: ; %for.end
; CHECK-NEXT:    ; in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT:    cmp x8, x1
; CHECK-NEXT:    add x8, x8, #1
; CHECK-NEXT:    b.eq LBB0_7
; CHECK-NEXT:  LBB0_2: ; %for.cond
; CHECK-NEXT:    ; =>This Loop Header: Depth=1
; CHECK-NEXT:    ; Child Loop BB0_3 Depth 2
; CHECK-NEXT:    cmp x8, x1
; CHECK-NEXT:    b.hs LBB0_8
; CHECK-NEXT:  LBB0_3: ; %for.body
; CHECK-NEXT:    ; Parent Loop BB0_2 Depth=1
; CHECK-NEXT:    ; => This Inner Loop Header: Depth=2
; CHECK-NEXT:    ldrb w9, [x0, x8]
; CHECK-NEXT:    cmp w9, #32
; CHECK-NEXT:    b.lo LBB0_1
; CHECK-NEXT:  ; %bb.4: ; %switch.test
; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=2
; CHECK-NEXT:    cmp w9, #34
; CHECK-NEXT:    b.eq LBB0_1
; CHECK-NEXT:  ; %bb.5: ; %switch.test
; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=2
; CHECK-NEXT:    cmp w9, #92
; CHECK-NEXT:    b.eq LBB0_1
; CHECK-NEXT:  ; %bb.6: ; %for.inc
; CHECK-NEXT:    ; in Loop: Header=BB0_3 Depth=2
; CHECK-NEXT:    add x9, x8, #1
; CHECK-NEXT:    cmp x9, x1
; CHECK-NEXT:    b.ne LBB0_3
; CHECK-NEXT:  LBB0_7:
; CHECK-NEXT:    mov w0, wzr
; CHECK-NEXT:    ret
; CHECK-NEXT:  LBB0_8:
; CHECK-NEXT:    mov w0, #1 ; =0x1
; CHECK-NEXT:    ret
  br label %for.cond

for.cond:
  %i = phi i64 [ 0, %0 ], [ %add, %for.end ]
  %cmp = icmp ult i64 %i, %len
  br i1 %cmp, label %for.body, label %ret1

for.body:
  %arrayidx = getelementptr inbounds i8, ptr %p, i64 %i
  %load = load i8, ptr %arrayidx, align 1
  %freeze = freeze i8 %load
  %cmp.lo = icmp ugt i8 %freeze, 31
  br i1 %cmp.lo, label %switch.test, label %for.end

switch.test:
  switch i8 %freeze, label %for.inc [
    i8 92, label %for.end
    i8 34, label %for.end
  ]

for.inc:
  %inc = add nuw i64 %i, 1
  %exitcond = icmp eq i64 %inc, %len
  br i1 %exitcond, label %ret0, label %for.body

for.end:
  %cmp.end = icmp eq i64 %i, %len
  %add = add i64 %i, 1
  br i1 %cmp.end, label %ret0, label %for.cond

ret0:
  ret i32 0

ret1:
  ret i32 1
}

define i32 @freeze_i8_load_loop(ptr %p, i32 %n) {
; CHECK-LABEL: freeze_i8_load_loop:
; CHECK:       ; %bb.0:
; CHECK-NEXT:    mov x8, x0
; CHECK-NEXT:    mov w0, wzr
; CHECK-NEXT:    mov w9, wzr
; CHECK-NEXT:    ldrb w8, [x8]
; CHECK-NEXT:  LBB1_1: ; %loop
; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    add w9, w9, #1
; CHECK-NEXT:    add w0, w0, w8
; CHECK-NEXT:    cmp w9, w1
; CHECK-NEXT:    b.lt LBB1_1
; CHECK-NEXT:  ; %bb.2: ; %exit
; CHECK-NEXT:    ret
  %load = load i8, ptr %p
  %freeze = freeze i8 %load
  %zext = zext i8 %freeze to i32
  br label %loop

loop:
  %acc = phi i32 [ 0, %0 ], [ %sum, %loop ]
  %i = phi i32 [ 0, %0 ], [ %inc, %loop ]
  %sum = add i32 %acc, %zext
  %inc = add i32 %i, 1
  %cmp = icmp slt i32 %inc, %n
  br i1 %cmp, label %loop, label %exit

exit:
  ret i32 %sum
}

define i32 @freeze_i16_load_cross_bb(ptr %p, i1 %cond) {
; CHECK-LABEL: freeze_i16_load_cross_bb:
; CHECK:       ; %bb.0: ; %common.ret
; CHECK-NEXT:    ldrh w8, [x0]
; CHECK-NEXT:    tst w1, #0x1
; CHECK-NEXT:    csel w0, w8, wzr, ne
; CHECK-NEXT:    ret
  %load = load i16, ptr %p
  %freeze = freeze i16 %load
  br i1 %cond, label %then, label %else

then:
  %zext = zext i16 %freeze to i32
  ret i32 %zext

else:
  ret i32 0
}

define i32 @freeze_non_load_cross_bb(i8 %val, i1 %cond) {
; CHECK-LABEL: freeze_non_load_cross_bb:
; CHECK:       ; %bb.0: ; %common.ret
; CHECK-NEXT:    and w8, w0, #0xff
; CHECK-NEXT:    tst w1, #0x1
; CHECK-NEXT:    csel w0, w8, wzr, ne
; CHECK-NEXT:    ret
  %freeze = freeze i8 %val
  br i1 %cond, label %then, label %else

then:
  %zext = zext i8 %freeze to i32
  ret i32 %zext

else:
  ret i32 0
}