derek.holloway
7502bf64a4
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198 lines
6.4 KiB
YAML
198 lines
6.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=early-machinelicm -o - %s | FileCheck %s
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# This test verifies that cross-bank copies (e.g., GPR to FPR, FPR to GPR)
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# are hoisted out of loops by MachineLICM, as they are expensive on AArch64.
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--- |
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declare void @use_float(float)
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declare void @use_int(i32)
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define void @gpr_to_fpr_virtual_copy_hoisted() {
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ret void
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}
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define void @gpr_to_fpr_physical_copy_hoisted() {
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ret void
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}
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define void @fpr_to_gpr_virtual_copy_hoisted() {
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ret void
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}
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...
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---
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name: gpr_to_fpr_virtual_copy_hoisted
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: gpr_to_fpr_virtual_copy_hoisted
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY $wzr
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY [[COPY2]]
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[COPY1]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32common = PHI [[COPY3]], %bb.0, %5, %bb.2
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; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[PHI]], [[COPY]], implicit-def $nzcv
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; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $s0 = COPY [[COPY4]]
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; CHECK-NEXT: BL @use_float, implicit-def dead $lr, implicit $sp, implicit $s0, implicit-def $sp
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; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[PHI]], 1, 0
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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liveins: $w0, $w1
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%1:gpr32 = COPY $w0
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%0:gpr32 = COPY $w1
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%3:gpr32all = COPY $wzr
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%2:gpr32all = COPY %3:gpr32all
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bb.1:
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%4:gpr32common = PHI %2:gpr32all, %bb.0, %5:gpr32all, %bb.2
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%6:gpr32 = SUBSWrr %4:gpr32common, %1:gpr32, implicit-def $nzcv
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Bcc 1, %bb.3, implicit $nzcv
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B %bb.2
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bb.2:
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%7:fpr32 = COPY %0:gpr32
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$s0 = COPY %7:fpr32
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BL @use_float, implicit-def dead $lr, implicit $sp, implicit $s0, implicit-def $sp
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%8:gpr32sp = ADDWri %4:gpr32common, 1, 0
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%5:gpr32all = COPY %8:gpr32sp
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B %bb.1
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bb.3:
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RET_ReallyLR
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...
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---
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name: gpr_to_fpr_physical_copy_hoisted
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: gpr_to_fpr_physical_copy_hoisted
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY $wzr
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $wzr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32common = PHI [[COPY2]], %bb.0, %4, %bb.2
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; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[PHI]], [[COPY]], implicit-def $nzcv
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; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $s0 = COPY [[COPY3]]
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; CHECK-NEXT: BL @use_float, implicit-def dead $lr, implicit $sp, implicit $s0, implicit-def $sp
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; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[PHI]], 1, 0
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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liveins: $w0
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%1:gpr32 = COPY $w0
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%3:gpr32all = COPY $wzr
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%2:gpr32all = COPY %3:gpr32all
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bb.1:
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%4:gpr32common = PHI %2:gpr32all, %bb.0, %5:gpr32all, %bb.2
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%6:gpr32 = SUBSWrr %4:gpr32common, %1:gpr32, implicit-def $nzcv
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Bcc 1, %bb.3, implicit $nzcv
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B %bb.2
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bb.2:
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%7:fpr32 = COPY $wzr
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$s0 = COPY %7:fpr32
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BL @use_float, implicit-def dead $lr, implicit $sp, implicit $s0, implicit-def $sp
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%8:gpr32sp = ADDWri %4:gpr32common, 1, 0
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%5:gpr32all = COPY %8:gpr32sp
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B %bb.1
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bb.3:
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RET_ReallyLR
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...
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---
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name: fpr_to_gpr_virtual_copy_hoisted
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: fpr_to_gpr_virtual_copy_hoisted
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $w0, $s0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY $wzr
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY [[COPY2]]
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY1]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32common = PHI [[COPY3]], %bb.0, %5, %bb.2
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; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[PHI]], [[COPY]], implicit-def $nzcv
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; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $w0 = COPY [[COPY4]]
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; CHECK-NEXT: BL @use_int, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp
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; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[PHI]], 1, 0
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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liveins: $w0, $s0
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%1:gpr32 = COPY $w0
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%0:fpr32 = COPY $s0
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%3:gpr32all = COPY $wzr
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%2:gpr32all = COPY %3:gpr32all
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bb.1:
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%4:gpr32common = PHI %2:gpr32all, %bb.0, %5:gpr32all, %bb.2
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%6:gpr32 = SUBSWrr %4:gpr32common, %1:gpr32, implicit-def $nzcv
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Bcc 1, %bb.3, implicit $nzcv
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B %bb.2
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bb.2:
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%7:gpr32 = COPY %0:fpr32
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$w0 = COPY %7:gpr32
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BL @use_int, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp
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%8:gpr32sp = ADDWri %4:gpr32common, 1, 0
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%5:gpr32all = COPY %8:gpr32sp
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B %bb.1
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bb.3:
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RET_ReallyLR
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...
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