TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/load-store-forwarding.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64 -global-isel=0 -o - %s | FileCheck %s --check-prefixes CHECK-LE,CHECK-SD
; RUN: llc -mtriple=aarch64_be -global-isel=0 -o - %s | FileCheck %s --check-prefixes CHECK-BE
; RUN: llc -mtriple=aarch64 -global-isel=1 -o - %s | FileCheck %s --check-prefixes CHECK-LE,CHECK-GI

define i8 @test1(i32 %a, ptr %pa) {
; CHECK-SD-LABEL: test1:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    str w0, [x1]
; CHECK-SD-NEXT:    ret
;
; CHECK-BE-LABEL: test1:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    mov w8, w0
; CHECK-BE-NEXT:    lsr w0, w0, #24
; CHECK-BE-NEXT:    str w8, [x1]
; CHECK-BE-NEXT:    ret
;
; CHECK-GI-LABEL: test1:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    str w0, [x1]
; CHECK-GI-NEXT:    and w0, w0, #0xff
; CHECK-GI-NEXT:    ret
  store i32 %a, ptr %pa
  %res = load i8, ptr %pa
  ret i8 %res
}

define i8 @test2(i32 %a, ptr %pa) {
; CHECK-LE-LABEL: test2:
; CHECK-LE:       // %bb.0:
; CHECK-LE-NEXT:    str w0, [x1]
; CHECK-LE-NEXT:    ubfx w0, w0, #8, #8
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: test2:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    str w0, [x1]
; CHECK-BE-NEXT:    ldrb w0, [x1, #1]
; CHECK-BE-NEXT:    ret
  %p8 = getelementptr i8, ptr %pa, i32 1
  store i32 %a, ptr %pa
  %res = load i8, ptr %p8
  ret i8 %res
}

define i8 @test3(i32 %a, ptr %pa) {
; CHECK-LE-LABEL: test3:
; CHECK-LE:       // %bb.0:
; CHECK-LE-NEXT:    str w0, [x1]
; CHECK-LE-NEXT:    ubfx w0, w0, #16, #8
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: test3:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    str w0, [x1]
; CHECK-BE-NEXT:    ldrb w0, [x1, #2]
; CHECK-BE-NEXT:    ret
  %p8 = getelementptr i8, ptr %pa, i32 2
  store i32 %a, ptr %pa
  %res = load i8, ptr %p8
  ret i8 %res
}

define i8 @test4(i32 %a, ptr %pa) {
; CHECK-LE-LABEL: test4:
; CHECK-LE:       // %bb.0:
; CHECK-LE-NEXT:    str w0, [x1]
; CHECK-LE-NEXT:    lsr w0, w0, #24
; CHECK-LE-NEXT:    ret
;
; CHECK-BE-LABEL: test4:
; CHECK-BE:       // %bb.0:
; CHECK-BE-NEXT:    str w0, [x1]
; CHECK-BE-NEXT:    ret
  %p8 = getelementptr i8, ptr %pa, i32 3
  store i32 %a, ptr %pa
  %res = load i8, ptr %p8
  ret i8 %res
}

define i32 @load_i16_store_i8(ptr %p, ptr %q) {
; CHECK-SD-LABEL: load_i16_store_i8:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    ldrb w8, [x0]
; CHECK-SD-NEXT:    mov w0, wzr
; CHECK-SD-NEXT:    strb w8, [x1]
; CHECK-SD-NEXT:    ret
;
; CHECK-BE-LABEL: load_i16_store_i8:
; CHECK-BE:       // %bb.0: // %entry
; CHECK-BE-NEXT:    ldrb w8, [x0, #1]
; CHECK-BE-NEXT:    mov w0, wzr
; CHECK-BE-NEXT:    strb w8, [x1]
; CHECK-BE-NEXT:    ret
;
; CHECK-GI-LABEL: load_i16_store_i8:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    ldrh w8, [x0]
; CHECK-GI-NEXT:    mov w0, wzr
; CHECK-GI-NEXT:    strb w8, [x1]
; CHECK-GI-NEXT:    ret
entry:
  %l = load i16, ptr %p, align 4
  %tr = trunc i16 %l to i8
  store i8 %tr, ptr %q, align 1
  ret i32 0
}

define i32 @load_i16_store_i8_freeze(ptr %p, ptr %q) {
; CHECK-SD-LABEL: load_i16_store_i8_freeze:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    ldrb w8, [x0]
; CHECK-SD-NEXT:    mov w0, wzr
; CHECK-SD-NEXT:    strb w8, [x1]
; CHECK-SD-NEXT:    ret
;
; CHECK-BE-LABEL: load_i16_store_i8_freeze:
; CHECK-BE:       // %bb.0: // %entry
; CHECK-BE-NEXT:    ldrb w8, [x0, #1]
; CHECK-BE-NEXT:    mov w0, wzr
; CHECK-BE-NEXT:    strb w8, [x1]
; CHECK-BE-NEXT:    ret
;
; CHECK-GI-LABEL: load_i16_store_i8_freeze:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    ldrh w8, [x0]
; CHECK-GI-NEXT:    mov w0, wzr
; CHECK-GI-NEXT:    strb w8, [x1]
; CHECK-GI-NEXT:    ret
entry:
  %l = load i16, ptr %p, align 4
  %fr = freeze i16 %l
  %tr = trunc i16 %fr to i8
  store i8 %tr, ptr %q, align 1
  ret i32 0
}