derek.holloway
7502bf64a4
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308 lines
15 KiB
YAML
308 lines
15 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=arm64-appe-ios -o - -run-pass=machine-combiner %s | FileCheck %s
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--- |
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define float @reassoicate_some_inputs_in_different_block(ptr %a, i1 %c) {
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ret float undef
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}
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define float @reassoicate_candidates_in_different_blocks(ptr %a, i1 %c) {
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ret float undef
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}
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define float @reassoicate_candidates_in_different_blocks_no_sink(ptr %a, i1 %c) {
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ret float undef
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}
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define float @no_reassociate_different_block(ptr %a, i1 %c) {
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ret float undef
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}
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declare void @use()
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...
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# FIXME: Should reassociate the serialized reduction in bb.1 to improve parallelism.
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---
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name: reassoicate_some_inputs_in_different_block
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alignment: 4
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: reassoicate_some_inputs_in_different_block
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui1:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 1 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui2:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 2 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui3:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 4 :: (load (s128), align 4)
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; CHECK-NEXT: TBZW [[COPY]], 0, %bb.2
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui]], [[LDRQui2]], implicit $fpcr
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; CHECK-NEXT: [[FADDv4f32_1:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui3]], [[LDRQui1]], implicit $fpcr
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; CHECK-NEXT: [[FADDv4f32_2:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 killed [[FADDv4f32_1]], killed [[FADDv4f32_]], implicit $fpcr
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; CHECK-NEXT: [[FADDPv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDPv4f32 [[FADDv4f32_2]], [[FADDv4f32_2]], implicit $fpcr
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[FADDPv4f32_]].dsub
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY2]]
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; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed [[COPY3]], implicit $fpcr
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; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: $q0 = COPY [[LDRQui]]
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; CHECK-NEXT: $q1 = COPY [[LDRQui2]]
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; CHECK-NEXT: $q2 = COPY [[LDRQui1]]
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; CHECK-NEXT: $q3 = COPY [[LDRQui3]]
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; CHECK-NEXT: TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $x0, $w1
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%5:gpr32 = COPY $w1
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%4:gpr64common = COPY $x0
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%0:fpr128 = LDRQui %4, 0 :: (load (s128), align 4)
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%1:fpr128 = LDRQui %4, 1 :: (load (s128), align 4)
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%2:fpr128 = LDRQui %4, 2 :: (load (s128), align 4)
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%3:fpr128 = LDRQui %4, 4 :: (load (s128), align 4)
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TBZW %5, 0, %bb.2
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B %bb.1
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bb.1:
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%6:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %0, %2, implicit $fpcr
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%7:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %1, killed %6, implicit $fpcr
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%8:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %3, killed %7, implicit $fpcr
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%9:fpr128 = nofpexcept FADDPv4f32 %8, %8, implicit $fpcr
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%10:gpr64all = COPY %9.dsub
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%12:fpr64 = COPY %10
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%11:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed %12, implicit $fpcr
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$s0 = COPY %11
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RET_ReallyLR implicit $s0
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bb.2:
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$q0 = COPY %0
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$q1 = COPY %2
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$q2 = COPY %1
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$q3 = COPY %3
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TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3
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...
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# Variation of reassoicate_some_inputs_in_different_block where the candidate
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# instructions are split across 2 blocks.
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---
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name: reassoicate_candidates_in_different_blocks
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alignment: 4
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: reassoicate_candidates_in_different_blocks
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui1:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 1 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui2:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 2 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui3:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 4 :: (load (s128), align 4)
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; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui]], [[LDRQui2]], implicit $fpcr
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; CHECK-NEXT: [[FADDv4f32_1:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui1]], killed [[FADDv4f32_]], implicit $fpcr
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; CHECK-NEXT: TBZW [[COPY]], 0, %bb.2
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: [[FADDv4f32_2:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui3]], killed [[FADDv4f32_1]], implicit $fpcr
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; CHECK-NEXT: [[FADDPv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDPv4f32 [[FADDv4f32_2]], [[FADDv4f32_2]], implicit $fpcr
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[FADDPv4f32_]].dsub
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY2]]
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; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed [[COPY3]], implicit $fpcr
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; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: $q0 = COPY [[LDRQui]]
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; CHECK-NEXT: $q1 = COPY [[LDRQui2]]
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; CHECK-NEXT: $q2 = COPY [[LDRQui1]]
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; CHECK-NEXT: $q3 = COPY [[LDRQui3]]
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; CHECK-NEXT: TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $x0, $w1
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%5:gpr32 = COPY $w1
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%4:gpr64common = COPY $x0
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%0:fpr128 = LDRQui %4, 0 :: (load (s128), align 4)
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%1:fpr128 = LDRQui %4, 1 :: (load (s128), align 4)
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%2:fpr128 = LDRQui %4, 2 :: (load (s128), align 4)
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%3:fpr128 = LDRQui %4, 4 :: (load (s128), align 4)
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%6:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %0, %2, implicit $fpcr
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%7:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %1, killed %6, implicit $fpcr
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TBZW %5, 0, %bb.2
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B %bb.1
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bb.1:
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%8:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %3, killed %7, implicit $fpcr
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%9:fpr128 = nofpexcept FADDPv4f32 %8, %8, implicit $fpcr
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%10:gpr64all = COPY %9.dsub
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%12:fpr64 = COPY %10
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%11:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed %12, implicit $fpcr
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$s0 = COPY %11
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RET_ReallyLR implicit $s0
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bb.2:
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$q0 = COPY %0
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$q1 = COPY %2
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$q2 = COPY %1
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$q3 = COPY %3
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TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3
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...
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---
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name: reassoicate_candidates_in_different_blocks_no_sink
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alignment: 4
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: reassoicate_candidates_in_different_blocks_no_sink
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui1:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 1 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui2:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 2 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui3:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 4 :: (load (s128), align 4)
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; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui]], [[LDRQui2]], implicit $fpcr
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; CHECK-NEXT: [[FADDv4f32_1:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui1]], killed [[FADDv4f32_]], implicit $fpcr
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; CHECK-NEXT: TBZW [[COPY]], 0, %bb.2
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: [[FADDv4f32_2:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui3]], killed [[FADDv4f32_1]], implicit $fpcr
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; CHECK-NEXT: [[FADDPv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDPv4f32 [[FADDv4f32_2]], [[FADDv4f32_2]], implicit $fpcr
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[FADDPv4f32_]].dsub
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY2]]
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; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed [[COPY3]], implicit $fpcr
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; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: $q0 = COPY [[LDRQui]]
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; CHECK-NEXT: $q1 = COPY [[LDRQui2]]
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; CHECK-NEXT: $q2 = COPY [[LDRQui1]]
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; CHECK-NEXT: $q3 = COPY [[FADDv4f32_1]]
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; CHECK-NEXT: TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $x0, $w1
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%5:gpr32 = COPY $w1
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%4:gpr64common = COPY $x0
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%0:fpr128 = LDRQui %4, 0 :: (load (s128), align 4)
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%1:fpr128 = LDRQui %4, 1 :: (load (s128), align 4)
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%2:fpr128 = LDRQui %4, 2 :: (load (s128), align 4)
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%3:fpr128 = LDRQui %4, 4 :: (load (s128), align 4)
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%6:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %0, %2, implicit $fpcr
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%7:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %1, killed %6, implicit $fpcr
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TBZW %5, 0, %bb.2
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B %bb.1
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bb.1:
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%8:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %3, killed %7, implicit $fpcr
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%9:fpr128 = nofpexcept FADDPv4f32 %8, %8, implicit $fpcr
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%10:gpr64all = COPY %9.dsub
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%12:fpr64 = COPY %10
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%11:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed %12, implicit $fpcr
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$s0 = COPY %11
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RET_ReallyLR implicit $s0
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bb.2:
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$q0 = COPY %0
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$q1 = COPY %2
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$q2 = COPY %1
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$q3 = COPY %7
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TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3
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...
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# Reassociation of the reduction in bb.1 is not profitable, because LDRQui3 has a
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# much larger latency than the other loads.
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---
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name: no_reassociate_different_block
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alignment: 4
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: no_reassociate_different_block
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-NEXT: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui1:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 1 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRQui2:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 2 :: (load (s128), align 4)
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; CHECK-NEXT: [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY1]], 8 :: (load (s64))
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; CHECK-NEXT: [[LDRXui1:%[0-9]+]]:gpr64common = LDRXui killed [[LDRXui]], 0 :: (load (s64))
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; CHECK-NEXT: [[LDRQui3:%[0-9]+]]:fpr128 = LDRQui killed [[LDRXui1]], 0 :: (load (s128), align 4)
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; CHECK-NEXT: TBZW [[COPY]], 0, %bb.2
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: [[FADDv4f32_:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui]], [[LDRQui2]], implicit $fpcr
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; CHECK-NEXT: [[FADDv4f32_1:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui1]], killed [[FADDv4f32_]], implicit $fpcr
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; CHECK-NEXT: [[FADDv4f32_2:%[0-9]+]]:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 [[LDRQui3]], killed [[FADDv4f32_1]], implicit $fpcr
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; CHECK-NEXT: [[FADDPv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDPv4f32 [[FADDv4f32_2]], [[FADDv4f32_2]], implicit $fpcr
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY [[FADDPv4f32_]].dsub
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY2]]
|
|
; CHECK-NEXT: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed [[COPY3]], implicit $fpcr
|
|
; CHECK-NEXT: $s0 = COPY [[FADDPv2i32p]]
|
|
; CHECK-NEXT: RET_ReallyLR implicit $s0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2:
|
|
; CHECK-NEXT: $q0 = COPY [[LDRQui]]
|
|
; CHECK-NEXT: $q1 = COPY [[LDRQui2]]
|
|
; CHECK-NEXT: $q2 = COPY [[LDRQui1]]
|
|
; CHECK-NEXT: $q3 = COPY [[LDRQui3]]
|
|
; CHECK-NEXT: TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3
|
|
bb.0:
|
|
successors: %bb.1, %bb.2
|
|
liveins: $x0, $w1
|
|
|
|
%5:gpr32 = COPY $w1
|
|
%4:gpr64common = COPY $x0
|
|
%0:fpr128 = LDRQui %4, 0 :: (load (s128), align 4)
|
|
%1:fpr128 = LDRQui %4, 1 :: (load (s128), align 4)
|
|
%2:fpr128 = LDRQui %4, 2 :: (load (s128), align 4)
|
|
%6:gpr64common = LDRXui %4, 8 :: (load (s64))
|
|
%7:gpr64common = LDRXui killed %6, 0 :: (load (s64))
|
|
%3:fpr128 = LDRQui killed %7, 0 :: (load (s128), align 4)
|
|
TBZW %5, 0, %bb.2
|
|
B %bb.1
|
|
|
|
bb.1:
|
|
%8:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %0, %2, implicit $fpcr
|
|
%9:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %1, killed %8, implicit $fpcr
|
|
%10:fpr128 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDv4f32 %3, killed %9, implicit $fpcr
|
|
%11:fpr128 = nofpexcept FADDPv4f32 %10, %10, implicit $fpcr
|
|
%12:gpr64all = COPY %11.dsub
|
|
%14:fpr64 = COPY %12
|
|
%13:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADDPv2i32p killed %14, implicit $fpcr
|
|
$s0 = COPY %13
|
|
RET_ReallyLR implicit $s0
|
|
|
|
bb.2:
|
|
$q0 = COPY %0
|
|
$q1 = COPY %2
|
|
$q2 = COPY %1
|
|
$q3 = COPY %3
|
|
TCRETURNdi @use, 0, csr_darwin_aarch64_aapcs, implicit $sp, implicit $q0, implicit $q1, implicit $q2, implicit $q3
|
|
|
|
...
|