derek.holloway
7502bf64a4
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77 lines
2.0 KiB
LLVM
77 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s
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; The test cases in this file check following transformation if the right form
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; can reduce latency.
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; A - (B + C) ==> (A - B) - C
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; 32 bit version.
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define i32 @test1(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add w8, w0, #100
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; CHECK-NEXT: orr w9, w2, #0x80
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; CHECK-NEXT: eor w10, w1, w8, lsl #8
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; CHECK-NEXT: sub w8, w9, w8
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; CHECK-NEXT: sub w8, w8, w10
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; CHECK-NEXT: eor w0, w8, w10, asr #13
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; CHECK-NEXT: ret
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entry:
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%c1 = or i32 %c, 128
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%a1 = add i32 %a, 100
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%shl = shl i32 %a1, 8
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%xor = xor i32 %shl, %b
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%add = add i32 %xor, %a1
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%sub = sub i32 %c1, %add
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%shr = ashr i32 %xor, 13
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%xor2 = xor i32 %sub, %shr
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ret i32 %xor2
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}
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; 64 bit version.
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define i64 @test2(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add x8, x0, #100
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; CHECK-NEXT: orr x9, x2, #0x80
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; CHECK-NEXT: eor x10, x1, x8, lsl #8
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; CHECK-NEXT: sub x8, x9, x8
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; CHECK-NEXT: sub x8, x8, x10
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; CHECK-NEXT: eor x0, x8, x10, asr #13
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; CHECK-NEXT: ret
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entry:
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%c1 = or i64 %c, 128
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%a1 = add i64 %a, 100
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%shl = shl i64 %a1, 8
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%xor = xor i64 %shl, %b
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%add = add i64 %xor, %a1
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%sub = sub i64 %c1, %add
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%shr = ashr i64 %xor, 13
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%xor2 = xor i64 %sub, %shr
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ret i64 %xor2
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}
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; Negative test. The right form can't reduce latency.
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define i32 @test3(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add w8, w0, #100
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; CHECK-NEXT: orr w9, w2, #0x80
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; CHECK-NEXT: eor w10, w1, w8, lsl #8
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; CHECK-NEXT: add w8, w9, w8
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; CHECK-NEXT: sub w8, w10, w8
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; CHECK-NEXT: eor w0, w8, w10, asr #13
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; CHECK-NEXT: ret
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entry:
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%c1 = or i32 %c, 128
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%a1 = add i32 %a, 100
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%shl = shl i32 %a1, 8
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%xor = xor i32 %shl, %b
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%add = add i32 %c1, %a1
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%sub = sub i32 %xor, %add
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%shr = ashr i32 %xor, 13
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%xor2 = xor i32 %sub, %shr
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ret i32 %xor2
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}
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