derek.holloway
7502bf64a4
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87 lines
3.4 KiB
LLVM
87 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple aarch64 -mattr=+sve < %s | FileCheck %s
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define <vscale x 4 x i16> @urem_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m) {
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; CHECK-LABEL: urem_nxv4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and z1.s, z1.s, #0xffff
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; CHECK-NEXT: mov z2.s, #1 // =0x1
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; CHECK-NEXT: and z0.s, z0.s, #0xffff
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; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: movprfx z2, z0
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; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z1.s
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; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i16> @llvm.masked.urem(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m)
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ret <vscale x 4 x i16> %res
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}
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define <vscale x 4 x i32> @urem_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m) {
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; CHECK-LABEL: urem_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z2.s, #1 // =0x1
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; CHECK-NEXT: sel z1.s, p0, z1.s, z2.s
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: movprfx z2, z0
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; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z1.s
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; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.masked.urem(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 8 x i32> @urem_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m) {
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; CHECK-LABEL: urem_nxv8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z4.s, #1 // =0x1
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; CHECK-NEXT: punpklo p1.h, p0.b
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; CHECK-NEXT: punpkhi p0.h, p0.b
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; CHECK-NEXT: sel z2.s, p1, z2.s, z4.s
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; CHECK-NEXT: sel z3.s, p0, z3.s, z4.s
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: movprfx z5, z0
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; CHECK-NEXT: udiv z5.s, p1/m, z5.s, z2.s
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; CHECK-NEXT: movprfx z4, z1
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; CHECK-NEXT: udiv z4.s, p1/m, z4.s, z3.s
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; CHECK-NEXT: mls z0.s, p1/m, z5.s, z2.s
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; CHECK-NEXT: mls z1.s, p1/m, z4.s, z3.s
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i32> @llvm.masked.urem(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m)
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ret <vscale x 8 x i32> %res
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}
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define <vscale x 8 x i16> @urem_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m) {
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; CHECK-LABEL: urem_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z2.h, #1 // =0x1
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; CHECK-NEXT: uunpklo z4.s, z0.h
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; CHECK-NEXT: sel z1.h, p0, z1.h, z2.h
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; CHECK-NEXT: uunpkhi z2.s, z0.h
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: uunpkhi z3.s, z1.h
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; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z3.s
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; CHECK-NEXT: uunpklo z3.s, z1.h
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; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h
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; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.masked.urem(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 2 x i64> @urem_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m) {
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; CHECK-LABEL: urem_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z2.d, #1 // =0x1
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; CHECK-NEXT: sel z1.d, p0, z1.d, z2.d
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: movprfx z2, z0
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; CHECK-NEXT: udiv z2.d, p0/m, z2.d, z1.d
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; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.masked.urem(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m)
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ret <vscale x 2 x i64> %res
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}
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