derek.holloway
7502bf64a4
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202 lines
5.2 KiB
YAML
202 lines
5.2 KiB
YAML
# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
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# RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
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# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck %s
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# RUN: llc -o - -passes=postmisched %s | FileCheck %s
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# REQUIRES: asserts
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# -misched=shuffle is only available with assertions enabled
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# Check that instructions that are recognized as branch targets by BTI
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# are not reordered by machine instruction schedulers.
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-gnu"
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define i32 @f_pac_pseudo(i32 %a, i32 %b, i32 %c) #0 "sign-return-address"="all" {
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entry:
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ret i32 0
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}
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define i32 @f_pac(i32 %a, i32 %b, i32 %c) #0 "sign-return-address"="all" {
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entry:
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ret i32 0
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}
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define i32 @f_bti(i32 %a, i32 %b, i32 %c) #0 {
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entry:
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ret i32 0
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}
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define i32 @f_brk(i32 %a, i32 %b, i32 %c) #0 {
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entry:
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ret i32 0
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}
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define i32 @f_hlt(i32 %a, i32 %b, i32 %c) #0 {
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entry:
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ret i32 0
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}
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define i32 @f_nop(i32 %a, i32 %b, i32 %c) #0 {
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entry:
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ret i32 0
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}
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attributes #0 = { nounwind memory(none) "target-features"="+v8.2a" }
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...
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---
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name: f_pac_pseudo
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0, $w1, $w2, $lr
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frame-setup PAUTH_PROLOGUE implicit-def $lr, implicit $lr, implicit $sp
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$w8 = ADDWrs $w0, $w1, 0
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$w0 = MADDWrrr $w8, $w2, $wzr
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RET undef $lr, implicit $w0
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# PAUTH_EPILOGUE instruction is omitted for simplicity as it is technically possible
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# to move it, so it may end up at a less obvious position in a basic block.
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# CHECK-LABEL: name: f_pac_pseudo
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# CHECK: body: |
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# CHECK-NEXT: bb.0.entry:
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# CHECK-NEXT: liveins: $w0, $w1, $w2, $lr
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#
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# CHECK: frame-setup PAUTH_PROLOGUE implicit-def $lr, implicit {{.*}}$lr, implicit $sp
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# CHECK-NEXT: $w8 = ADDWrs {{.*}}$w0, {{.*}}$w1, 0
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# CHECK-NEXT: $w0 = MADDWrrr {{.*}}$w8, {{.*}}$w2, $wzr
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# CHECK-NEXT: RET undef $lr, implicit {{.*}}$w0
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...
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---
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name: f_pac
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0, $w1, $w2, $lr
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frame-setup PACIASP implicit-def $lr, implicit $lr, implicit $sp
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$w8 = ADDWrs $w0, $w1, 0
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$w0 = MADDWrrr $w8, $w2, $wzr
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RET undef $lr, implicit $w0
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# AUTIASP is omitted, see above.
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# CHECK-LABEL: name: f_pac
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# CHECK: body: |
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# CHECK-NEXT: bb.0.entry:
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# CHECK-NEXT: liveins: $w0, $w1, $w2, $lr
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#
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# CHECK: frame-setup PACIASP implicit-def $lr, implicit {{.*}}$lr, implicit $sp
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# CHECK-NEXT: $w8 = ADDWrs {{.*}}$w0, {{.*}}$w1, 0
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# CHECK-NEXT: $w0 = MADDWrrr {{.*}}$w8, {{.*}}$w2, $wzr
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# CHECK-NEXT: RET undef $lr, implicit {{.*}}$w0
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...
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---
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name: f_bti
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0, $w1, $w2, $lr
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HINT 34
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$w8 = ADDWrs $w0, $w1, 0
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$w0 = MADDWrrr $w8, $w2, $wzr
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RET undef $lr, implicit $w0
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# CHECK-LABEL: name: f_bti
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# CHECK: body: |
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# CHECK-NEXT: bb.0.entry:
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# CHECK-NEXT: liveins: $w0, $w1, $w2, $lr
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#
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# CHECK: HINT 34
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# CHECK-NEXT: $w8 = ADDWrs {{.*}}$w0, {{.*}}$w1, 0
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# CHECK-NEXT: $w0 = MADDWrrr {{.*}}$w8, {{.*}}$w2, $wzr
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# CHECK-NEXT: RET undef $lr, implicit {{.*}}$w0
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...
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---
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name: f_brk
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0, $w1, $w2, $lr
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BRK 1
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$w8 = ADDWrs $w0, $w1, 0
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$w0 = MADDWrrr $w8, $w2, $wzr
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RET undef $lr, implicit $w0
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# CHECK-LABEL: name: f_brk
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# CHECK: body: |
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# CHECK-NEXT: bb.0.entry:
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# CHECK-NEXT: liveins: $w0, $w1, $w2, $lr
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#
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# CHECK: BRK 1
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# CHECK-NEXT: $w8 = ADDWrs {{.*}}$w0, {{.*}}$w1, 0
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# CHECK-NEXT: $w0 = MADDWrrr {{.*}}$w8, {{.*}}$w2, $wzr
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# CHECK-NEXT: RET undef $lr, implicit {{.*}}$w0
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...
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---
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name: f_hlt
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0, $w1, $w2, $lr
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HLT 1
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$w8 = ADDWrs $w0, $w1, 0
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$w0 = MADDWrrr $w8, $w2, $wzr
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RET undef $lr, implicit $w0
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# CHECK-LABEL: name: f_hlt
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# CHECK: body: |
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# CHECK-NEXT: bb.0.entry:
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# CHECK-NEXT: liveins: $w0, $w1, $w2, $lr
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#
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# CHECK: HLT 1
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# CHECK-NEXT: $w8 = ADDWrs {{.*}}$w0, {{.*}}$w1, 0
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# CHECK-NEXT: $w0 = MADDWrrr {{.*}}$w8, {{.*}}$w2, $wzr
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# CHECK-NEXT: RET undef $lr, implicit {{.*}}$w0
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...
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---
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name: f_nop
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $w0, $w1, $w2, $lr
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HINT 0
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$w8 = ADDWrs $w0, $w1, 0
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$w0 = MADDWrrr $w8, $w2, $wzr
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RET undef $lr, implicit $w0
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# Check that BTI-related instructions are left intact not because *anything*
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# is left intact.
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# CHECK-LABEL: name: f_nop
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# CHECK: body: |
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# CHECK-NEXT: bb.0.entry:
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# CHECK-NEXT: liveins: $w0, $w1, $w2, $lr
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#
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# CHECK: $w8 = ADDWrs {{.*}}$w0, {{.*}}$w1, 0
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# CHECK-DAG: $w0 = MADDWrrr {{.*}}$w8, {{.*}}$w2, $wzr
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# CHECK-DAG: HINT 0
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# CHECK-NEXT: RET undef $lr, implicit {{.*}}$w0
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...
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