derek.holloway
7502bf64a4
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66 lines
3.3 KiB
LLVM
66 lines
3.3 KiB
LLVM
; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=fuse-csel -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a78 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a710 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a715 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a720 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a725 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-x4 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-x925 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n2 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n3 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v1 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v2 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-v3 -debug-only=machine-scheduler 2>&1 | FileCheck %s
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; REQUIRES: asserts
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; Check that the scheduling model has an edge between the SUBS and the CSEL.
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; CHECK-LABEL: test_sub_cselw:%bb.0
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; CHECK: SU(2): %3:gpr32common = ADDWri %1:gpr32common, 7, 0
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; CHECK: SU(3): dead $wzr = SUBSWri %0:gpr32common, 13, 0, implicit-def $nzcv
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; CHECK: Successors:
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; CHECK: SU(4): Ord Latency=0 Cluster
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; CHECK: SU(4): %5:gpr32 = CSELWr %0:gpr32common, %3:gpr32common, 0, implicit killed $nzcv
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; CHECK: Predecessors:
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; CHECK: SU(3): Ord Latency=0 Cluster
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; CHECK: SU(5): $w0 = COPY %5:gpr32
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; CHECK-LABEL: test_sub_cselx:%bb.0
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; CHECK: SU(2): %3:gpr64common = ADDXri %1:gpr64common, 7, 0
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; CHECK: SU(3): dead $xzr = SUBSXri %0:gpr64common, 13, 0, implicit-def $nzcv
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; CHECK: Successors:
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; CHECK: SU(4): Ord Latency=0 Cluster
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; CHECK: SU(4): %5:gpr64 = CSELXr %0:gpr64common, %3:gpr64common, 0, implicit killed $nzcv
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; CHECK: Predecessors:
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; CHECK: SU(3): Ord Latency=0 Cluster
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; CHECK: SU(5): $x0 = COPY %5:gpr64
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define i32 @test_sub_cselw(i32 %a0, i32 %a1, i32 %a2) {
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entry:
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%v0 = sub i32 %a0, 13
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%cond = icmp eq i32 %v0, 0
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%v1 = add i32 %a1, 7
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%v2 = select i1 %cond, i32 %a0, i32 %v1
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ret i32 %v2
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; CHECK-LABEL: test_sub_cselw:
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; CHECK: cmp {{w[0-9]}}, #13
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; CHECK-NEXT: csel {{w[0-9]}}
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}
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define i64 @test_sub_cselx(i64 %a0, i64 %a1, i64 %a2) {
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entry:
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%v0 = sub i64 %a0, 13
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%cond = icmp eq i64 %v0, 0
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%v1 = add i64 %a1, 7
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%v2 = select i1 %cond, i64 %a0, i64 %v1
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ret i64 %v2
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; CHECK-LABEL: test_sub_cselx:
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; CHECK: cmp {{x[0-9]}}, #13
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; CHECK-NEXT: csel {{x[0-9]}}
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}
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