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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/mul-i256.ll
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derek.holloway 7502bf64a4
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

125 lines
3.3 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
; i256 multiply
define i256 @mul_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: mul_i256:
; CHECK: // %bb.0:
; CHECK-NEXT: umulh x8, x4, x2
; CHECK-NEXT: umulh x9, x6, x0
; CHECK-NEXT: madd x8, x4, x3, x8
; CHECK-NEXT: madd x9, x6, x1, x9
; CHECK-NEXT: mul x10, x4, x2
; CHECK-NEXT: mul x11, x6, x0
; CHECK-NEXT: madd x8, x5, x2, x8
; CHECK-NEXT: madd x9, x7, x0, x9
; CHECK-NEXT: adds x10, x11, x10
; CHECK-NEXT: umulh x13, x0, x4
; CHECK-NEXT: mul x14, x1, x4
; CHECK-NEXT: adc x8, x9, x8
; CHECK-NEXT: umulh x12, x1, x4
; CHECK-NEXT: mul x16, x0, x5
; CHECK-NEXT: adds x9, x14, x13
; CHECK-NEXT: umulh x15, x0, x5
; CHECK-NEXT: cinc x12, x12, hs
; CHECK-NEXT: mul x11, x1, x5
; CHECK-NEXT: umulh x17, x1, x5
; CHECK-NEXT: adds x1, x16, x9
; CHECK-NEXT: cinc x9, x15, hs
; CHECK-NEXT: mul x0, x0, x4
; CHECK-NEXT: adds x9, x12, x9
; CHECK-NEXT: cset w12, hs
; CHECK-NEXT: adds x9, x11, x9
; CHECK-NEXT: adc x11, x17, x12
; CHECK-NEXT: adds x2, x9, x10
; CHECK-NEXT: adc x3, x11, x8
; CHECK-NEXT: ret
%r = mul i256 %a, %b
ret i256 %r
}
; i256 multiply by constant
define i256 @mul_i256_const(i256 %a) nounwind {
; CHECK-LABEL: mul_i256_const:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #42 // =0x2a
; CHECK-NEXT: umulh x13, x0, x8
; CHECK-NEXT: mul x14, x1, x8
; CHECK-NEXT: umulh x11, x1, x8
; CHECK-NEXT: mul x12, x2, x8
; CHECK-NEXT: adds x1, x14, x13
; CHECK-NEXT: mul x9, x3, x8
; CHECK-NEXT: umulh x10, x2, x8
; CHECK-NEXT: adcs x2, x12, x11
; CHECK-NEXT: mul x0, x0, x8
; CHECK-NEXT: adc x3, x10, x9
; CHECK-NEXT: ret
%r = mul i256 %a, 42
ret i256 %r
}
; i256 add
define i256 @add_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: add_i256:
; CHECK: // %bb.0:
; CHECK-NEXT: adds x0, x0, x4
; CHECK-NEXT: adcs x1, x1, x5
; CHECK-NEXT: adcs x2, x2, x6
; CHECK-NEXT: adc x3, x3, x7
; CHECK-NEXT: ret
%r = add i256 %a, %b
ret i256 %r
}
; i256 sub
define i256 @sub_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: sub_i256:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x0, x0, x4
; CHECK-NEXT: sbcs x1, x1, x5
; CHECK-NEXT: sbcs x2, x2, x6
; CHECK-NEXT: sbc x3, x3, x7
; CHECK-NEXT: ret
%r = sub i256 %a, %b
ret i256 %r
}
; i256 and
define i256 @and_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: and_i256:
; CHECK: // %bb.0:
; CHECK-NEXT: and x2, x2, x6
; CHECK-NEXT: and x0, x0, x4
; CHECK-NEXT: and x1, x1, x5
; CHECK-NEXT: and x3, x3, x7
; CHECK-NEXT: ret
%r = and i256 %a, %b
ret i256 %r
}
; i256 or
define i256 @or_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: or_i256:
; CHECK: // %bb.0:
; CHECK-NEXT: orr x2, x2, x6
; CHECK-NEXT: orr x0, x0, x4
; CHECK-NEXT: orr x1, x1, x5
; CHECK-NEXT: orr x3, x3, x7
; CHECK-NEXT: ret
%r = or i256 %a, %b
ret i256 %r
}
; i256 xor
define i256 @xor_i256(i256 %a, i256 %b) nounwind {
; CHECK-LABEL: xor_i256:
; CHECK: // %bb.0:
; CHECK-NEXT: eor x2, x2, x6
; CHECK-NEXT: eor x0, x0, x4
; CHECK-NEXT: eor x1, x1, x5
; CHECK-NEXT: eor x3, x3, x7
; CHECK-NEXT: ret
%r = xor i256 %a, %b
ret i256 %r
}