derek.holloway
7502bf64a4
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174 lines
6.1 KiB
LLVM
174 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; VECTOR_SPLICE (index)
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;
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define <16 x i8> @splice_v16i8_idx(<16 x i8> %a, <16 x i8> %b) #0 {
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; CHECK-LABEL: splice_v16i8_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #1
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; CHECK-NEXT: ret
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%res = call <16 x i8> @llvm.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1)
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ret <16 x i8> %res
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}
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define <2 x double> @splice_v2f64_idx(<2 x double> %a, <2 x double> %b) #0 {
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; CHECK-LABEL: splice_v2f64_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8
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; CHECK-NEXT: ret
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%res = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 1)
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ret <2 x double> %res
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}
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; Verify promote type legalisation works as expected.
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define <2 x i8> @splice_v2i8_idx(<2 x i8> %a, <2 x i8> %b) #0 {
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; CHECK-LABEL: splice_v2i8_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4
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; CHECK-NEXT: ret
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%res = call <2 x i8> @llvm.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 1)
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ret <2 x i8> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <8 x i32> @splice_v8i32_idx(<8 x i32> %a, <8 x i32> %b) #0 {
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; CHECK-LABEL: splice_v8i32_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4
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; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4
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; CHECK-NEXT: ret
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%res = call <8 x i32> @llvm.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 5)
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ret <8 x i32> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <16 x float> @splice_v16f32_idx(<16 x float> %a, <16 x float> %b) #0 {
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; CHECK-LABEL: splice_v16f32_idx:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v6.16b, v3.16b, v4.16b, #12
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; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12
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; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #12
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; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12
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; CHECK-NEXT: mov v2.16b, v6.16b
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; CHECK-NEXT: ret
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%res = call <16 x float> @llvm.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 7)
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ret <16 x float> %res
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}
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;
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; VECTOR_SPLICE (trailing elements)
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;
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define <16 x i8> @splice_v16i8(<16 x i8> %a, <16 x i8> %b) #0 {
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; CHECK-LABEL: splice_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #1
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; CHECK-NEXT: ret
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%res = call <16 x i8> @llvm.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 -15)
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ret <16 x i8> %res
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}
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define <2 x double> @splice_v2f64(<2 x double> %a, <2 x double> %b) #0 {
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; CHECK-LABEL: splice_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8
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; CHECK-NEXT: ret
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%res = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 -1)
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ret <2 x double> %res
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}
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; Verify promote type legalisation works as expected.
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define <2 x i8> @splice_v2i8(<2 x i8> %a, <2 x i8> %b) #0 {
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; CHECK-LABEL: splice_v2i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4
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; CHECK-NEXT: ret
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%res = call <2 x i8> @llvm.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 -1)
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ret <2 x i8> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <8 x i32> @splice_v8i32(<8 x i32> %a, <8 x i32> %b) #0 {
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; CHECK-LABEL: splice_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4
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; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4
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; CHECK-NEXT: ret
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%res = call <8 x i32> @llvm.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 -3)
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ret <8 x i32> %res
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}
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; Verify splitvec type legalisation works as expected.
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define <16 x float> @splice_v16f32(<16 x float> %a, <16 x float> %b) #0 {
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; CHECK-LABEL: splice_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v6.16b, v3.16b, v4.16b, #12
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; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #12
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; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #12
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; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12
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; CHECK-NEXT: mov v2.16b, v6.16b
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; CHECK-NEXT: ret
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%res = call <16 x float> @llvm.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 -9)
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ret <16 x float> %res
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}
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; Check splice.right with 0 offset returns second operand.
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define <16 x i8> @splice_right_0(<16 x i8> %a, <16 x i8> %b) #0 {
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; CHECK-LABEL: splice_right_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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%res = call <16 x i8> @llvm.vector.splice.right(<16 x i8> %a, <16 x i8> %b, i32 0)
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ret <16 x i8> %res
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}
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define <4 x i32> @splice_left_v4i32_variable_offset(<4 x i32> %a, <4 x i32> %b, i32 zeroext %offset) #0 {
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; CHECK-LABEL: splice_left_v4i32_variable_offset:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: ubfiz x8, x0, #2, #32
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; CHECK-NEXT: mov w9, #16 // =0x10
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; CHECK-NEXT: cmp x8, #16
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; CHECK-NEXT: stp q0, q1, [sp, #-32]!
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; CHECK-NEXT: csel x8, x8, x9, lo
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: ldr q0, [x9, x8]
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%res = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %a, <4 x i32> %b, i32 %offset)
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ret <4 x i32> %res
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}
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define <4 x i32> @splice_right_v4i32_variable_offset(<4 x i32> %a, <4 x i32> %b, i32 zeroext %offset) #0 {
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; CHECK-LABEL: splice_right_v4i32_variable_offset:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: ubfiz x8, x0, #2, #32
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; CHECK-NEXT: mov w9, #16 // =0x10
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; CHECK-NEXT: mov x10, sp
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; CHECK-NEXT: stp q0, q1, [sp]
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; CHECK-NEXT: cmp x8, #16
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; CHECK-NEXT: csel x8, x8, x9, lo
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; CHECK-NEXT: add x9, x10, #16
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; CHECK-NEXT: sub x8, x9, x8
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; CHECK-NEXT: ldr q0, [x8]
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%res = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %a, <4 x i32> %b, i32 %offset)
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ret <4 x i32> %res
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}
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declare <2 x i8> @llvm.vector.splice.v2i8(<2 x i8>, <2 x i8>, i32)
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declare <16 x i8> @llvm.vector.splice.v16i8(<16 x i8>, <16 x i8>, i32)
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declare <8 x i32> @llvm.vector.splice.v8i32(<8 x i32>, <8 x i32>, i32)
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declare <16 x float> @llvm.vector.splice.v16f32(<16 x float>, <16 x float>, i32)
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declare <2 x double> @llvm.vector.splice.v2f64(<2 x double>, <2 x double>, i32)
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attributes #0 = { nounwind "target-features"="+neon" }
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