derek.holloway
7502bf64a4
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146 lines
5.6 KiB
LLVM
146 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple aarch64-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple aarch64-linux-gnu %s -o - -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; CHECK-GI: warning: Instruction selection used fallback path for any_of_select_vf2
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; CHECK-GI-NEXT: warning: Instruction selection used fallback path for any_of_select_vf32
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;; An 'AnyOf' reduction (vector.reduce.or) is instcombined to a bitcast to an
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;; integer of a bitwidth equal to the number of lanes being reduced, then
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;; compared against zero. To select between vectors for NEON, we then need to
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;; broadcast the result, but we must be careful when the bitwidth of the scalar
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;; result is smaller than the element size of the vectors being selected. We
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;; don't want to end up with scalarization.
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define <4 x i32> @any_of_select_vf4(<4 x i32> %mask, <4 x i32> %a, <4 x i32> %b) {
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; CHECK-SD-LABEL: any_of_select_vf4:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-SD-NEXT: movi d3, #0000000000000000
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; CHECK-SD-NEXT: addp d0, v0.2d
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; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, v3.2d
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; CHECK-SD-NEXT: dup v0.2d, v0.d[0]
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; CHECK-SD-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: any_of_select_vf4:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sub sp, sp, #16
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; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: mov w8, v0.s[1]
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; CHECK-GI-NEXT: mov w9, v0.s[2]
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; CHECK-GI-NEXT: fmov w11, s0
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; CHECK-GI-NEXT: mov w10, v0.s[3]
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; CHECK-GI-NEXT: and w8, w8, #0x1
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; CHECK-GI-NEXT: bfi w11, w8, #1, #31
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; CHECK-GI-NEXT: and w8, w9, #0x1
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; CHECK-GI-NEXT: and w9, w10, #0x1
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; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
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; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
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; CHECK-GI-NEXT: strb w8, [sp, #15]
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; CHECK-GI-NEXT: and w8, w8, #0xff
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; CHECK-GI-NEXT: tst w8, #0xf
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; CHECK-GI-NEXT: cset w8, eq
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; CHECK-GI-NEXT: sbfx w8, w8, #0, #1
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; CHECK-GI-NEXT: dup v0.4s, w8
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; CHECK-GI-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-GI-NEXT: add sp, sp, #16
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %mask, zeroinitializer
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%cmp.bc = bitcast <4 x i1> %cmp to i4
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%cmp.bc.not = icmp eq i4 %cmp.bc, 0
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%res = select i1 %cmp.bc.not, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %res
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}
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define <4 x i8> @any_of_select_v4i8(<4 x i32> %mask, <4 x i8> %a, <4 x i8> %b) {
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; CHECK-SD-LABEL: any_of_select_v4i8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-SD-NEXT: movi d3, #0000000000000000
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; CHECK-SD-NEXT: addp d0, v0.2d
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; CHECK-SD-NEXT: cmeq d0, d0, d3
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; CHECK-SD-NEXT: bsl v0.8b, v1.8b, v2.8b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: any_of_select_v4i8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sub sp, sp, #16
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; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: mov w8, v0.s[1]
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; CHECK-GI-NEXT: mov w9, v0.s[2]
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; CHECK-GI-NEXT: fmov w11, s0
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; CHECK-GI-NEXT: mov w10, v0.s[3]
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; CHECK-GI-NEXT: and w8, w8, #0x1
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; CHECK-GI-NEXT: bfi w11, w8, #1, #31
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; CHECK-GI-NEXT: and w8, w9, #0x1
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; CHECK-GI-NEXT: and w9, w10, #0x1
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; CHECK-GI-NEXT: orr w8, w11, w8, lsl #2
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; CHECK-GI-NEXT: orr w8, w8, w9, lsl #3
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; CHECK-GI-NEXT: mov w9, #255 // =0xff
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; CHECK-GI-NEXT: fmov s3, w9
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; CHECK-GI-NEXT: strb w8, [sp, #15]
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; CHECK-GI-NEXT: and w8, w8, #0xff
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; CHECK-GI-NEXT: tst w8, #0xf
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; CHECK-GI-NEXT: cset w8, eq
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; CHECK-GI-NEXT: mov v3.h[1], w9
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; CHECK-GI-NEXT: sbfx w8, w8, #0, #1
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; CHECK-GI-NEXT: fmov s0, w8
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; CHECK-GI-NEXT: mov v3.h[2], w9
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; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
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; CHECK-GI-NEXT: mov v3.h[3], w9
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; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
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; CHECK-GI-NEXT: zip1 v0.8b, v0.8b, v0.8b
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; CHECK-GI-NEXT: eor v3.8b, v0.8b, v3.8b
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; CHECK-GI-NEXT: and v0.8b, v1.8b, v0.8b
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; CHECK-GI-NEXT: and v1.8b, v2.8b, v3.8b
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; CHECK-GI-NEXT: orr v0.8b, v0.8b, v1.8b
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; CHECK-GI-NEXT: add sp, sp, #16
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %mask, zeroinitializer
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%cmp.bc = bitcast <4 x i1> %cmp to i4
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%cmp.bc.not = icmp eq i4 %cmp.bc, 0
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%res = select i1 %cmp.bc.not, <4 x i8> %a, <4 x i8> %b
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ret <4 x i8> %res
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}
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define <2 x i64> @any_of_select_vf2(<2 x i64> %mask, <2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: any_of_select_vf2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.2d, v0.2d, #0
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; CHECK-NEXT: movi d3, #0000000000000000
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; CHECK-NEXT: addp d0, v0.2d
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; CHECK-NEXT: cmeq v0.2d, v0.2d, v3.2d
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; CHECK-NEXT: dup v0.2d, v0.d[0]
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; CHECK-NEXT: bsl v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%cmp = icmp slt <2 x i64> %mask, zeroinitializer
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%cmp.bc = bitcast <2 x i1> %cmp to i2
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%cmp.bc.not = icmp eq i2 %cmp.bc, 0
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%res = select i1 %cmp.bc.not, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %res
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}
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define <32 x i8> @any_of_select_vf32(<32 x i8> %mask, <32 x i8> %a, <32 x i8> %b) {
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; CHECK-LABEL: any_of_select_vf32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: umaxv b0, v0.16b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: tst w8, #0x1
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; CHECK-NEXT: csetm w8, ne
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; CHECK-NEXT: dup v1.16b, w8
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: bsl v1.16b, v5.16b, v3.16b
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; CHECK-NEXT: bsl v0.16b, v4.16b, v2.16b
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; CHECK-NEXT: ret
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%cmp = icmp slt <32 x i8> %mask, zeroinitializer
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%cmp.bc = bitcast <32 x i1> %cmp to i32
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%cmp.bc.not = icmp eq i32 %cmp.bc, 0
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%res = select i1 %cmp.bc.not, <32 x i8> %a, <32 x i8> %b
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ret <32 x i8> %res
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}
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