derek.holloway
7502bf64a4
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709 lines
28 KiB
LLVM
709 lines
28 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s --check-prefixes=CHECK-LE,CHECK-SD
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; RUN: llc -mtriple aarch64-none-linux-gnu -mattr=+dotprod -global-isel < %s | FileCheck %s --check-prefixes=CHECK-LE,CHECK-GI
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; RUN: llc -mtriple aarch64_be-none-linux-gnu -mattr=+dotprod < %s | FileCheck %s --check-prefix=CHECK-BE
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define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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; CHECK-LE-LABEL: test_vdot_u32:
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; CHECK-LE: // %bb.0: // %entry
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; CHECK-LE-NEXT: udot v0.2s, v1.8b, v2.8b
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; CHECK-LE-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdot_u32:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v2.8b, v2.8b
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; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: udot v0.2s, v1.8b, v2.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: ret
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entry:
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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; CHECK-LE-LABEL: test_vdotq_u32:
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; CHECK-LE: // %bb.0: // %entry
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; CHECK-LE-NEXT: udot v0.4s, v1.16b, v2.16b
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; CHECK-LE-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdotq_u32:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v2.16b, v2.16b
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; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
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; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: udot v0.4s, v1.16b, v2.16b
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: ret
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entry:
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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; CHECK-LE-LABEL: test_vdot_s32:
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; CHECK-LE: // %bb.0: // %entry
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; CHECK-LE-NEXT: sdot v0.2s, v1.8b, v2.8b
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; CHECK-LE-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdot_s32:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v2.8b, v2.8b
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; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: sdot v0.2s, v1.8b, v2.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: ret
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entry:
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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; CHECK-LE-LABEL: test_vdotq_s32:
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; CHECK-LE: // %bb.0: // %entry
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; CHECK-LE-NEXT: sdot v0.4s, v1.16b, v2.16b
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; CHECK-LE-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdotq_s32:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v2.16b, v2.16b
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; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
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; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: sdot v0.4s, v1.16b, v2.16b
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: ret
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entry:
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_u32_zero(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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; CHECK-SD-LABEL: test_vdot_u32_zero:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: udot v0.2s, v1.8b, v2.8b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test_vdot_u32_zero:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
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; CHECK-GI-NEXT: udot v3.2s, v1.8b, v2.8b
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; CHECK-GI-NEXT: add v0.2s, v3.2s, v0.2s
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; CHECK-GI-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdot_u32_zero:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v2.8b, v2.8b
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; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: udot v0.2s, v1.8b, v2.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: ret
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entry:
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %c) #2
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%ret = add <2 x i32> %vdot1.i, %a
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ret <2 x i32> %ret
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}
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define <4 x i32> @test_vdotq_u32_zero(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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; CHECK-SD-LABEL: test_vdotq_u32_zero:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: udot v0.4s, v1.16b, v2.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test_vdotq_u32_zero:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
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; CHECK-GI-NEXT: udot v3.4s, v1.16b, v2.16b
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; CHECK-GI-NEXT: add v0.4s, v3.4s, v0.4s
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; CHECK-GI-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdotq_u32_zero:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v2.16b, v2.16b
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; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
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; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: udot v0.4s, v1.16b, v2.16b
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: ret
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entry:
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %c) #2
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%ret = add <4 x i32> %vdot1.i, %a
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ret <4 x i32> %ret
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}
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define <2 x i32> @test_vdot_s32_zero(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) #0 {
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; CHECK-SD-LABEL: test_vdot_s32_zero:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sdot v0.2s, v1.8b, v2.8b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test_vdot_s32_zero:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
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; CHECK-GI-NEXT: sdot v3.2s, v1.8b, v2.8b
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; CHECK-GI-NEXT: add v0.2s, v3.2s, v0.2s
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; CHECK-GI-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdot_s32_zero:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v2.8b, v2.8b
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; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: sdot v0.2s, v1.8b, v2.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: ret
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entry:
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %c) #2
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%ret = add <2 x i32> %vdot1.i, %a
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ret <2 x i32> %ret
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}
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define <4 x i32> @test_vdotq_s32_zero(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) #0 {
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; CHECK-SD-LABEL: test_vdotq_s32_zero:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: sdot v0.4s, v1.16b, v2.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test_vdotq_s32_zero:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
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; CHECK-GI-NEXT: sdot v3.4s, v1.16b, v2.16b
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; CHECK-GI-NEXT: add v0.4s, v3.4s, v0.4s
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; CHECK-GI-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdotq_s32_zero:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v2.16b, v2.16b
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; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
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; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: sdot v0.4s, v1.16b, v2.16b
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: ret
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entry:
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %c) #2
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%ret = add <4 x i32> %vdot1.i, %a
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ret <4 x i32> %ret
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}
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define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
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; CHECK-LE-LABEL: test_vdot_lane_u32:
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; CHECK-LE: // %bb.0: // %entry
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; CHECK-LE-NEXT: // kill: def $d2 killed $d2 def $q2
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; CHECK-LE-NEXT: udot v0.2s, v1.8b, v2.4b[1]
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; CHECK-LE-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdot_lane_u32:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: rev64 v2.2s, v2.2s
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; CHECK-BE-NEXT: udot v0.2s, v1.8b, v2.4b[1]
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: ret
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entry:
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
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%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
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%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
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ret <2 x i32> %vdot1.i
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}
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define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
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; CHECK-LE-LABEL: test_vdotq_lane_u32:
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; CHECK-LE: // %bb.0: // %entry
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; CHECK-LE-NEXT: // kill: def $d2 killed $d2 def $q2
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; CHECK-LE-NEXT: udot v0.4s, v1.16b, v2.4b[1]
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; CHECK-LE-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdotq_lane_u32:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: // kill: def $d2 killed $d2 def $q2
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; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
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; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: udot v0.4s, v1.16b, v2.4b[1]
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; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
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; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-BE-NEXT: ret
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entry:
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%.cast = bitcast <8 x i8> %c to <2 x i32>
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%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
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%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
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ret <4 x i32> %vdot1.i
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}
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define <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
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; CHECK-LE-LABEL: test_vdot_laneq_u32:
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; CHECK-LE: // %bb.0: // %entry
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; CHECK-LE-NEXT: udot v0.2s, v1.8b, v2.4b[1]
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; CHECK-LE-NEXT: ret
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;
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; CHECK-BE-LABEL: test_vdot_laneq_u32:
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; CHECK-BE: // %bb.0: // %entry
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; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
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; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
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; CHECK-BE-NEXT: udot v0.2s, v1.8b, v2.4b[1]
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; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
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; CHECK-BE-NEXT: ret
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entry:
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%.cast = bitcast <16 x i8> %c to <4 x i32>
|
|
%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
|
|
%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
|
|
%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
|
|
ret <2 x i32> %vdot1.i
|
|
}
|
|
|
|
define <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
|
|
; CHECK-LE-LABEL: test_vdotq_laneq_u32:
|
|
; CHECK-LE: // %bb.0: // %entry
|
|
; CHECK-LE-NEXT: udot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-LE-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdotq_laneq_u32:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
|
|
; CHECK-BE-NEXT: udot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <16 x i8> %c to <4 x i32>
|
|
%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
|
|
%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
|
|
ret <4 x i32> %vdot1.i
|
|
}
|
|
|
|
|
|
define <2 x i32> @test_vdot_lane_u32_zero(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
|
|
; CHECK-SD-LABEL: test_vdot_lane_u32_zero:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-SD-NEXT: udot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test_vdot_lane_u32_zero:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
|
|
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-GI-NEXT: udot v3.2s, v1.8b, v2.4b[1]
|
|
; CHECK-GI-NEXT: add v0.2s, v3.2s, v0.2s
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdot_lane_u32_zero:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: rev64 v2.2s, v2.2s
|
|
; CHECK-BE-NEXT: udot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <8 x i8> %c to <2 x i32>
|
|
%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
|
|
%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
|
|
%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %.cast5) #2
|
|
%ret = add <2 x i32> %vdot1.i, %a
|
|
ret <2 x i32> %ret
|
|
}
|
|
|
|
define <4 x i32> @test_vdotq_lane_u32_zero(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
|
|
; CHECK-SD-LABEL: test_vdotq_lane_u32_zero:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-SD-NEXT: udot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test_vdotq_lane_u32_zero:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
|
|
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-GI-NEXT: udot v3.4s, v1.16b, v2.4b[1]
|
|
; CHECK-GI-NEXT: add v0.4s, v3.4s, v0.4s
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdotq_lane_u32_zero:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: udot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <8 x i8> %c to <2 x i32>
|
|
%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
|
|
%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %.cast3) #2
|
|
%ret = add <4 x i32> %vdot1.i, %a
|
|
ret <4 x i32> %ret
|
|
}
|
|
|
|
define <2 x i32> @test_vdot_laneq_u32_zero(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
|
|
; CHECK-SD-LABEL: test_vdot_laneq_u32_zero:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: udot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test_vdot_laneq_u32_zero:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
|
|
; CHECK-GI-NEXT: udot v3.2s, v1.8b, v2.4b[1]
|
|
; CHECK-GI-NEXT: add v0.2s, v3.2s, v0.2s
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdot_laneq_u32_zero:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
|
|
; CHECK-BE-NEXT: udot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <16 x i8> %c to <4 x i32>
|
|
%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
|
|
%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
|
|
%vdot1.i = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %.cast5) #2
|
|
%ret = add <2 x i32> %vdot1.i, %a
|
|
ret <2 x i32> %ret
|
|
}
|
|
|
|
define <4 x i32> @test_vdotq_laneq_u32_zero(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
|
|
; CHECK-SD-LABEL: test_vdotq_laneq_u32_zero:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: udot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test_vdotq_laneq_u32_zero:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
|
|
; CHECK-GI-NEXT: udot v3.4s, v1.16b, v2.4b[1]
|
|
; CHECK-GI-NEXT: add v0.4s, v3.4s, v0.4s
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdotq_laneq_u32_zero:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
|
|
; CHECK-BE-NEXT: udot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <16 x i8> %c to <4 x i32>
|
|
%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
|
|
%vdot1.i = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %.cast3) #2
|
|
%ret = add <4 x i32> %vdot1.i, %a
|
|
ret <4 x i32> %ret
|
|
}
|
|
|
|
|
|
define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
|
|
; CHECK-LE-LABEL: test_vdot_lane_s32:
|
|
; CHECK-LE: // %bb.0: // %entry
|
|
; CHECK-LE-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-LE-NEXT: sdot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-LE-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdot_lane_s32:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: rev64 v2.2s, v2.2s
|
|
; CHECK-BE-NEXT: sdot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <8 x i8> %c to <2 x i32>
|
|
%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
|
|
%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
|
|
%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
|
|
ret <2 x i32> %vdot1.i
|
|
}
|
|
|
|
define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
|
|
; CHECK-LE-LABEL: test_vdotq_lane_s32:
|
|
; CHECK-LE: // %bb.0: // %entry
|
|
; CHECK-LE-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-LE-NEXT: sdot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-LE-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdotq_lane_s32:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: sdot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <8 x i8> %c to <2 x i32>
|
|
%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
|
|
%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
|
|
ret <4 x i32> %vdot1.i
|
|
}
|
|
|
|
define <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
|
|
; CHECK-LE-LABEL: test_vdot_laneq_s32:
|
|
; CHECK-LE: // %bb.0: // %entry
|
|
; CHECK-LE-NEXT: sdot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-LE-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdot_laneq_s32:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
|
|
; CHECK-BE-NEXT: sdot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <16 x i8> %c to <4 x i32>
|
|
%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
|
|
%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
|
|
%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %.cast5) #2
|
|
ret <2 x i32> %vdot1.i
|
|
}
|
|
|
|
define <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
|
|
; CHECK-LE-LABEL: test_vdotq_laneq_s32:
|
|
; CHECK-LE: // %bb.0: // %entry
|
|
; CHECK-LE-NEXT: sdot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-LE-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdotq_laneq_s32:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
|
|
; CHECK-BE-NEXT: sdot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <16 x i8> %c to <4 x i32>
|
|
%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
|
|
%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %.cast3) #2
|
|
ret <4 x i32> %vdot1.i
|
|
}
|
|
|
|
|
|
define <2 x i32> @test_vdot_lane_s32_zero(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c) {
|
|
; CHECK-SD-LABEL: test_vdot_lane_s32_zero:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-SD-NEXT: sdot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test_vdot_lane_s32_zero:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
|
|
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-GI-NEXT: sdot v3.2s, v1.8b, v2.4b[1]
|
|
; CHECK-GI-NEXT: add v0.2s, v3.2s, v0.2s
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdot_lane_s32_zero:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: rev64 v2.2s, v2.2s
|
|
; CHECK-BE-NEXT: sdot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <8 x i8> %c to <2 x i32>
|
|
%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
|
|
%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
|
|
%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %.cast5) #2
|
|
%ret = add <2 x i32> %vdot1.i, %a
|
|
ret <2 x i32> %ret
|
|
}
|
|
|
|
define <4 x i32> @test_vdotq_lane_s32_zero(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c) {
|
|
; CHECK-SD-LABEL: test_vdotq_lane_s32_zero:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-SD-NEXT: sdot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test_vdotq_lane_s32_zero:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
|
|
; CHECK-GI-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-GI-NEXT: sdot v3.4s, v1.16b, v2.4b[1]
|
|
; CHECK-GI-NEXT: add v0.4s, v3.4s, v0.4s
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdotq_lane_s32_zero:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: // kill: def $d2 killed $d2 def $q2
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: sdot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <8 x i8> %c to <2 x i32>
|
|
%shuffle = shufflevector <2 x i32> %.cast, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
|
|
%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %.cast3) #2
|
|
%ret = add <4 x i32> %vdot1.i, %a
|
|
ret <4 x i32> %ret
|
|
}
|
|
|
|
define <2 x i32> @test_vdot_laneq_s32_zero(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c) {
|
|
; CHECK-SD-LABEL: test_vdot_laneq_s32_zero:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: sdot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test_vdot_laneq_s32_zero:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
|
|
; CHECK-GI-NEXT: sdot v3.2s, v1.8b, v2.4b[1]
|
|
; CHECK-GI-NEXT: add v0.2s, v3.2s, v0.2s
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdot_laneq_s32_zero:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
|
|
; CHECK-BE-NEXT: sdot v0.2s, v1.8b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <16 x i8> %c to <4 x i32>
|
|
%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
|
|
%.cast5 = bitcast <2 x i32> %shuffle to <8 x i8>
|
|
%vdot1.i = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> zeroinitializer, <8 x i8> %b, <8 x i8> %.cast5) #2
|
|
%ret = add <2 x i32> %vdot1.i, %a
|
|
ret <2 x i32> %ret
|
|
}
|
|
|
|
define <4 x i32> @test_vdotq_laneq_s32_zero(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c) {
|
|
; CHECK-SD-LABEL: test_vdotq_laneq_s32_zero:
|
|
; CHECK-SD: // %bb.0: // %entry
|
|
; CHECK-SD-NEXT: sdot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test_vdotq_laneq_s32_zero:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
|
|
; CHECK-GI-NEXT: sdot v3.4s, v1.16b, v2.4b[1]
|
|
; CHECK-GI-NEXT: add v0.4s, v3.4s, v0.4s
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: test_vdotq_laneq_s32_zero:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v1.16b, v1.16b
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: rev64 v2.4s, v2.4s
|
|
; CHECK-BE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ext v2.16b, v2.16b, v2.16b, #8
|
|
; CHECK-BE-NEXT: sdot v0.4s, v1.16b, v2.4b[1]
|
|
; CHECK-BE-NEXT: rev64 v0.4s, v0.4s
|
|
; CHECK-BE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%.cast = bitcast <16 x i8> %c to <4 x i32>
|
|
%shuffle = shufflevector <4 x i32> %.cast, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
|
|
%.cast3 = bitcast <4 x i32> %shuffle to <16 x i8>
|
|
%vdot1.i = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> zeroinitializer, <16 x i8> %b, <16 x i8> %.cast3) #2
|
|
%ret = add <4 x i32> %vdot1.i, %a
|
|
ret <4 x i32> %ret
|
|
}
|
|
|
|
define <2 x i32> @be_vdot_lane_s32(<2 x i32> %r_val, <8 x i8> %a_val, <8 x i8> %b_val) {
|
|
; CHECK-LE-LABEL: be_vdot_lane_s32:
|
|
; CHECK-LE: // %bb.0: // %entry
|
|
; CHECK-LE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-LE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECK-LE-NEXT: rev64 v2.8b, v2.8b
|
|
; CHECK-LE-NEXT: sdot v0.2s, v1.8b, v2.4b[0]
|
|
; CHECK-LE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-LE-NEXT: ret
|
|
;
|
|
; CHECK-BE-LABEL: be_vdot_lane_s32:
|
|
; CHECK-BE: // %bb.0: // %entry
|
|
; CHECK-BE-NEXT: rev64 v2.8b, v2.8b
|
|
; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: rev64 v2.8b, v2.8b
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: rev64 v1.8b, v1.8b
|
|
; CHECK-BE-NEXT: rev32 v2.16b, v2.16b
|
|
; CHECK-BE-NEXT: sdot v0.2s, v1.8b, v2.4b[0]
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: rev64 v0.2s, v0.2s
|
|
; CHECK-BE-NEXT: ret
|
|
entry:
|
|
%shuffle = shufflevector <2 x i32> %r_val, <2 x i32> poison, <2 x i32> <i32 1, i32 0>
|
|
%shuffle1 = shufflevector <8 x i8> %a_val, <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
|
|
%shuffle2 = shufflevector <8 x i8> %b_val, <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 poison, i32 poison, i32 poison, i32 poison>
|
|
%0 = bitcast <8 x i8> %shuffle2 to <2 x i32>
|
|
%lane = shufflevector <2 x i32> %0, <2 x i32> poison, <2 x i32> zeroinitializer
|
|
%1 = bitcast <2 x i32> %lane to <8 x i8>
|
|
%vdot1.i = tail call noundef <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %shuffle, <8 x i8> %shuffle1, <8 x i8> %1)
|
|
%shuffle4 = shufflevector <2 x i32> %vdot1.i, <2 x i32> poison, <2 x i32> <i32 1, i32 0>
|
|
ret <2 x i32> %shuffle4
|
|
}
|