derek.holloway
7502bf64a4
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145 lines
5.1 KiB
LLVM
145 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <4 x i16> @shuffle1(<4 x i16> %v) {
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; CHECK-LABEL: shuffle1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: dup v0.2s, v0.s[0]
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 1>
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ret <4 x i16> %res
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}
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define <4 x i16> @shuffle2(<4 x i16> %v) {
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; CHECK-LABEL: shuffle2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: dup v0.2s, v0.s[1]
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 3>
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ret <4 x i16> %res
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}
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define <8 x i16> @shuffle3(<8 x i16> %v) {
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; CHECK-LABEL: shuffle3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: dup v0.2d, v0.d[0]
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 2, i32 3,
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i32 undef, i32 1, i32 undef, i32 3>
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ret <8 x i16> %res
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}
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define <4 x i32> @shuffle4(<4 x i32> %v) {
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; CHECK-LABEL: shuffle4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: dup v0.2d, v0.d[0]
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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ret <4 x i32> %res
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}
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define <16 x i8> @shuffle5(<16 x i8> %v) {
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; CHECK-LABEL: shuffle5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: dup v0.4s, v0.s[2]
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <16 x i8> %v, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11,
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i32 8, i32 9, i32 10, i32 11,
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i32 8, i32 9, i32 10, i32 11,
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i32 8, i32 9, i32 10, i32 11>
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ret <16 x i8> %res
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}
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define <16 x i8> @shuffle6(<16 x i8> %v) {
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; CHECK-LABEL: shuffle6:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: dup v0.2d, v0.d[1]
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <16 x i8> %v, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11,
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i32 12, i32 13, i32 14, i32 15,
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i32 8, i32 9, i32 10, i32 11,
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i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %res
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}
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define <8 x i8> @shuffle7(<8 x i8> %v) {
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; CHECK-LABEL: shuffle7:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: dup v0.2s, v0.s[1]
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <8 x i8> %v, <8 x i8> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 undef,
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i32 undef, i32 5, i32 6, i32 undef>
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ret <8 x i8> %res
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}
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define <8 x i8> @shuffle8(<8 x i8> %v) {
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; CHECK-LABEL: shuffle8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: dup v0.4h, v0.h[3]
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <8 x i8> %v, <8 x i8> undef, <8 x i32> <i32 6, i32 7, i32 6, i32 undef,
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i32 undef, i32 7, i32 6, i32 undef>
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ret <8 x i8> %res
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}
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; No blocks
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define <8 x i8> @shuffle_not1(<16 x i8> %v) {
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; CHECK-LABEL: shuffle_not1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #2
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-NEXT: ret
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%res = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
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ret <8 x i8> %res
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}
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; Block is not a proper lane
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define <4 x i32> @shuffle_not2(<4 x i32> %v) {
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; CHECK-LABEL: shuffle_not2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov v0.s[3], v0.s[2]
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; CHECK-NEXT: uzp2 v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 1, i32 2>
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ret <4 x i32> %res
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}
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; Block size is equal to vector size
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define <4 x i16> @shuffle_not3(<4 x i16> %v) {
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; CHECK-LABEL: shuffle_not3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i16> %res
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}
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; Blocks mismatch
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define <8 x i8> @shuffle_not4(<8 x i8> %v) {
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; CHECK-LABEL: shuffle_not4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: adrp x8, .LCPI11_0
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; CHECK-NEXT: mov v0.d[1], v0.d[0]
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI11_0]
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; CHECK-NEXT: tbl v0.8b, { v0.16b }, v1.8b
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <8 x i8> %v, <8 x i8> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 undef,
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i32 undef, i32 5, i32 5, i32 undef>
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ret <8 x i8> %res
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}
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