derek.holloway
7502bf64a4
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179 lines
6.7 KiB
LLVM
179 lines
6.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <4 x half> @shuffle1(<2 x half> %a, <2 x half> %b) {
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; CHECK-LABEL: shuffle1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: zip1 v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 2, i32 3, i32 0, i32 undef>
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ret <4 x half> %res
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}
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define <4 x half> @shuffle2(<2 x half> %a, <2 x half> %b) {
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; CHECK-LABEL: shuffle2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: zip1 v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <2 x half> %a, <2 x half> %b, <4 x i32> <i32 undef, i32 1, i32 2, i32 undef>
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ret <4 x half> %res
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}
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define <4 x i32> @shuffle3(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: shuffle3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: zip2 v0.2d, v1.2d, v0.2d
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
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ret <4 x i32> %res
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}
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define <4 x float> @shuffle4(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: shuffle4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov v0.d[1], v1.d[1]
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x float> %res
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}
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define <16 x i8> @shuffle5(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: shuffle5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 4, i32 5,
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i32 8, i32 9, i32 12, i32 13,
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i32 16, i32 17, i32 20, i32 21,
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i32 24, i32 25, i32 28, i32 29>
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ret <16 x i8> %res
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}
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define <16 x i8> @shuffle6(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: shuffle6:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: trn1 v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17,
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i32 4, i32 5, i32 20, i32 21,
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i32 8, i32 9, i32 24, i32 25,
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i32 12, i32 13, i32 28, i32 29>
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ret <16 x i8> %res
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}
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define <8 x i8> @shuffle7(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: shuffle7:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: uzp2 v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 6, i32 undef,
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i32 undef, i32 11, i32 14, i32 undef>
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ret <8 x i8> %res
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}
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define <8 x i8> @shuffle8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: shuffle8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: trn2 v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 10, i32 undef,
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i32 undef, i32 7, i32 14, i32 undef>
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ret <8 x i8> %res
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}
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; No blocks
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define <8 x i8> @shuffle9(<8 x i8> %a) {
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; CHECK-LABEL: shuffle9:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev32 v0.4h, v0.4h
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; CHECK-NEXT: ret
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%res = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 0, i32 1,
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i32 6, i32 7, i32 4, i32 5>
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ret <8 x i8> %res
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}
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define <8 x i16> @shuffle10(<8 x i16> %a) {
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; CHECK-LABEL: shuffle10:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rev64 v0.4s, v0.4s
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; CHECK-NEXT: ret
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%res = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 2, i32 3, i32 0, i32 1,
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i32 undef, i32 undef, i32 4, i32 5>
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ret <8 x i16> %res
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}
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define <4 x i16> @shuffle11(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: shuffle11:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: zip1 v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <8 x i16> %a, <8 x i16> %b, <4 x i32> <i32 8, i32 9, i32 0, i32 1>
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ret <4 x i16> %res
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}
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define <8 x i8> @shuffle12(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: shuffle12:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: trn2 v0.4h, v0.4h, v0.4h
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 4, i32 5, i32 4, i32 undef,
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i32 undef, i32 13, i32 12, i32 undef>
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ret <8 x i8> %res
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}
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define <8 x i16> @shuffle_widen_faili1(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: shuffle_widen_faili1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI12_0
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; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI12_0]
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
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; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 7, i32 6, i32 0, i32 1,
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i32 3, i32 2, i32 4, i32 5>
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ret <8 x i16> %res
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}
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define <8 x i16> @shuffle_widen_fail2(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: shuffle_widen_fail2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI13_0
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; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_0]
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; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1
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; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 6, i32 6, i32 0, i32 1,
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i32 undef, i32 2, i32 4, i32 5>
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ret <8 x i16> %res
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}
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define <8 x i16> @shuffle_widen_fail3(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: shuffle_widen_fail3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: adrp x8, .LCPI14_0
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; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_0]
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; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
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; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
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; CHECK-NEXT: ret
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entry:
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%res = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 5, i32 12, i32 14,
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i32 10, i32 6, i32 7, i32 13>
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ret <8 x i16> %res
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}
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