derek.holloway
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114 lines
3.6 KiB
YAML
114 lines
3.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -o - -mtriple=aarch64-unknown-linux -run-pass=aarch64-mi-peephole-opt -verify-machineinstrs | FileCheck %s
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# RUN: llc %s -o - -mtriple=aarch64-unknown-linux -passes=aarch64-mi-peephole-opt | FileCheck %s
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---
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name: peephole_cselxr_same
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registers:
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- { id: 1, class: gpr64, preferred-register: '' }
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- { id: 2, class: gpr64, preferred-register: '' }
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liveins:
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- { reg: '$x0', virtual-reg: '%1' }
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- { reg: '$x1', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK-LABEL: name: peephole_cselxr_same
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[ORRXrs:%[0-9]+]]:gpr64 = ORRXrs $xzr, [[COPY1]], 0
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; CHECK-NEXT: RET_ReallyLR
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%3:gpr64 = COPY $x1
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%4:gpr64 = COPY $x0
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$xzr = ANDSXri %3, 0, implicit-def $nzcv
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%5:gpr64 = CSELXr %4, %4, 0, implicit $nzcv
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RET_ReallyLR
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...
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---
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name: peephole_cselwr_same
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registers:
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- { id: 1, class: gpr32, preferred-register: '' }
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- { id: 2, class: gpr32, preferred-register: '' }
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liveins:
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- { reg: '$w0', virtual-reg: '%1' }
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- { reg: '$w1', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: peephole_cselwr_same
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY1]], 0
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; CHECK-NEXT: RET_ReallyLR
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%3:gpr32 = COPY $w1
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%4:gpr32 = COPY $w0
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$wzr = ANDSWri %3, 0, implicit-def $nzcv
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%5:gpr32 = CSELWr %4, %4, 0, implicit $nzcv
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RET_ReallyLR
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...
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---
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name: peephole_cselxr_different
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registers:
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- { id: 1, class: gpr64, preferred-register: '' }
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- { id: 2, class: gpr64, preferred-register: '' }
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liveins:
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- { reg: '$x0', virtual-reg: '%1' }
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- { reg: '$x1', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $x0, $x1
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; CHECK-LABEL: name: peephole_cselxr_different
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY]], [[COPY1]], 0, implicit $nzcv
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; CHECK-NEXT: RET_ReallyLR
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%3:gpr64 = COPY $x1
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%4:gpr64 = COPY $x0
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$xzr = ANDSXri %3, 0, implicit-def $nzcv
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%5:gpr64 = CSELXr %3, %4, 0, implicit $nzcv
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RET_ReallyLR
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...
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---
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name: peephole_cselwr_different
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registers:
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- { id: 1, class: gpr32, preferred-register: '' }
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- { id: 2, class: gpr32, preferred-register: '' }
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liveins:
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- { reg: '$w0', virtual-reg: '%1' }
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- { reg: '$w1', virtual-reg: '%2' }
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body: |
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bb.0.entry:
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liveins: $w0, $w1
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; CHECK-LABEL: name: peephole_cselwr_different
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
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; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY]], [[COPY1]], 0, implicit $nzcv
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; CHECK-NEXT: RET_ReallyLR
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%3:gpr32 = COPY $w1
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%4:gpr32 = COPY $w0
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$wzr = ANDSWri %3, 0, implicit-def $nzcv
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%5:gpr32 = CSELWr %3, %4, 0, implicit $nzcv
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RET_ReallyLR
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...
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