TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/peephole-sxtw.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
# RUN: llc -passes=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux %s | FileCheck %s

---
name: removeSxtw
tracksRegLiveness: true
body: |
  bb.0.entry:
    liveins: $x0
    ; CHECK-LABEL: name: removeSxtw
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
    ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY1]], 1, 0
    ; CHECK-NEXT: $w0 = COPY [[ADDWri]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr64 = COPY $x0
    %1:gpr64 = SBFMXri %0:gpr64, 0, 31
    %2:gpr32sp = COPY %1.sub_32:gpr64
    %3:gpr32sp = ADDWri %2:gpr32sp, 1, 0
    $w0 = COPY %3:gpr32sp
    RET_ReallyLR implicit $w0
...
---
name: extraCopy
tracksRegLiveness: true
body: |
  bb.0.entry:
    liveins: $x0
    ; CHECK-LABEL: name: extraCopy
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
    ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY1]], 1, 0
    ; CHECK-NEXT: $w0 = COPY [[ADDWri]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr64 = COPY $x0
    %1:gpr64 = SBFMXri %0:gpr64, 0, 31
    %2:gpr64all = COPY %1:gpr64
    %3:gpr32sp = COPY %2.sub_32:gpr64all
    %4:gpr32sp = ADDWri %3:gpr32sp, 1, 0
    $w0 = COPY %4:gpr32sp
    RET_ReallyLR implicit $w0
...
---
name: multipleCopies
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: multipleCopies
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $w0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
  ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
  ; CHECK-NEXT:   [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY2]], [[COPY1]]
  ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[SUBWrr]], %subreg.sub_32
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   successors: %bb.1(0x04000000), %bb.2(0x7c000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   CBZX [[SUBREG_TO_REG]], %bb.1
  ; CHECK-NEXT:   B %bb.2
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $w0

    %2:gpr32 = COPY $w0
    %4:gpr64all = IMPLICIT_DEF
    %3:gpr64 = INSERT_SUBREG %4, %2, %subreg.sub_32
    %5:gpr64 = SBFMXri killed %3, 0, 31
    %0:gpr64all = COPY %5
    %6:gpr64all = COPY %0
    %7:gpr32 = COPY %6.sub_32
    %8:gpr32 = COPY $wzr
    %9:gpr32 = SUBWrr %8, %7
    %10:gpr32 = ORRWrs $wzr, %9, 0
    %1:gpr64 = SUBREG_TO_REG %10, %subreg.sub_32

  bb.1:
    successors: %bb.2(0x80000000)

  bb.2:
    successors: %bb.1(0x04000000), %bb.2(0x7c000000)

    CBZX %1, %bb.1
    B %bb.2

...
---
name: removeUxtw
tracksRegLiveness: true
body: |
  bb.0.entry:
    liveins: $x0
    ; CHECK-LABEL: name: removeUxtw
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
    ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY2]], 1, 0
    ; CHECK-NEXT: $w0 = COPY [[ADDWri]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr64 = COPY $x0
    %1:gpr32 = COPY %0.sub_32
    %2:gpr32 = ORRWrr $wzr, %1
    %3:gpr64 = SUBREG_TO_REG %2, %subreg.sub_32
    %4:gpr32sp = COPY %3.sub_32
    %5:gpr32sp = ADDWri %4, 1, 0
    $w0 = COPY %5
    RET_ReallyLR implicit $w0
...
---
name: extraUseOrr
tracksRegLiveness: true
body: |
  bb.0.entry:
    liveins: $x0
    ; CHECK-LABEL: name: extraUseOrr
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]].sub_32
    ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr $wzr, [[COPY1]]
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG [[ORRWrr]], %subreg.sub_32
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32
    ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY2]], 1, 0
    ; CHECK-NEXT: $w0 = COPY [[ADDWri]]
    ; CHECK-NEXT: $w1 = COPY [[ORRWrr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %0:gpr64 = COPY $x0
    %1:gpr32 = COPY %0.sub_32
    %2:gpr32 = ORRWrr $wzr, %1
    %3:gpr64 = SUBREG_TO_REG %2, %subreg.sub_32
    %4:gpr32sp = COPY %3.sub_32
    %5:gpr32sp = ADDWri %4, 1, 0
    $w0 = COPY %5
    $w1 = COPY %2
    RET_ReallyLR implicit $w0
...