derek.holloway
7502bf64a4
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88 lines
3.4 KiB
YAML
88 lines
3.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=aarch64 -mattr=+sme2 -force-streaming -start-before=greedy -stop-after=virtregrewriter %s -o - | FileCheck %s
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# Check the register allocator gets hints to reuse registers of one of its operands.
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---
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name: prioritize_movprfx_hints
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tracksRegLiveness: true
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isSSA: false
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noVRegs: false
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body: |
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bb.0.entry:
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liveins: $z0, $z1, $z2, $z3, $p0
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; CHECK-LABEL: name: prioritize_movprfx_hints
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; CHECK: liveins: $p0, $z0, $z1, $z2, $z3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $z0 = SDIV_ZPZZ_D_UNDEF $p0, killed renamable $z0, killed renamable $z1
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; CHECK-NEXT: renamable $z2 = MUL_ZPZZ_D_UNDEF $p0, killed renamable $z2, killed renamable $z3
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; CHECK-NEXT: renamable $z0 = MUL_ZPZZ_D_UNDEF $p0, killed renamable $z2, killed renamable $z0
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; CHECK-NEXT: RET_ReallyLR implicit $z0
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%0:zpr = COPY $z3
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%1:zpr = COPY $z2
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%2:zpr = COPY $z1
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%3:zpr = COPY $z0
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%4:zpr = SDIV_ZPZZ_D_UNDEF $p0, %3:zpr, %2:zpr
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%5:zpr = MUL_ZPZZ_D_UNDEF $p0, %1:zpr, %0:zpr
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%6:zpr = MUL_ZPZZ_D_UNDEF $p0, %5:zpr, %4:zpr
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$z0 = COPY %6:zpr
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RET_ReallyLR implicit $z0
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...
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# Check the register allocator prioritises hints that are set by the register
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# allocator itself (i.e. to use z4 for the result register).
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---
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name: prioritize_regalloc_hints
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isSSA: false
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noVRegs: false
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: prioritize_regalloc_hints
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; CHECK: renamable $z0 = FDUP_ZI_S 0, implicit $vg
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; CHECK-NEXT: renamable $z1 = FDUP_ZI_S 16, implicit $vg
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; CHECK-NEXT: renamable $z2 = FDUP_ZI_S 32, implicit $vg
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; CHECK-NEXT: renamable $p0 = PTRUE_S 31, implicit $vg
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; CHECK-NEXT: renamable $z4 = FMLA_ZPZZZ_S_UNDEF killed renamable $p0, killed renamable $z0, killed renamable $z1, killed renamable $z2
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; CHECK-NEXT: RET_ReallyLR implicit $z4
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%0:zpr = FDUP_ZI_S 0, implicit $vg
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%1:zpr = FDUP_ZI_S 16, implicit $vg
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%2:zpr = FDUP_ZI_S 32, implicit $vg
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%3:ppr_3b = PTRUE_S 31, implicit $vg
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%4:zpr = FMLA_ZPZZZ_S_UNDEF %3, %0, %1, %2
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$z4 = COPY %4
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RET_ReallyLR implicit $z4
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...
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# Check the register allocator gets hints to reuse registers of one of its
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# operands, which are a subreg of a multi-register RegisterClass.
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---
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name: prioritize_subreg_hints
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tracksRegLiveness: true
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isSSA: false
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noVRegs: false
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $x2
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; CHECK-LABEL: name: prioritize_subreg_hints
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; CHECK: liveins: $x0, $x1, $x2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $pn8 = PTRUE_C_B implicit $vg
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; CHECK-NEXT: renamable $z16_z24 = LD1B_2Z_IMM_PSEUDO killed renamable $pn8, killed renamable $x2, 0
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; CHECK-NEXT: renamable $z16 = ADD_ZI_B_PSEUDO renamable $z16, 5, 0
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; CHECK-NEXT: renamable $z24 = ADD_ZI_B_PSEUDO killed renamable $z24, 5, 0
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; CHECK-NEXT: STR_ZXI killed renamable $z16, killed renamable $x0, 0
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; CHECK-NEXT: STR_ZXI killed renamable $z24, killed renamable $x1, 0
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; CHECK-NEXT: RET_ReallyLR
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%0:gpr64common = COPY $x0
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%1:gpr64common = COPY $x1
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%2:gpr64common = COPY $x2
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%3:pnr_p8to15 = PTRUE_C_B implicit $vg
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%4:zpr2stridedorcontiguous = LD1B_2Z_IMM_PSEUDO %3, %2, 0
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%7:zpr = ADD_ZI_B_PSEUDO %4.zsub0, 5, 0
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%8:zpr = ADD_ZI_B_PSEUDO %4.zsub1, 5, 0
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STR_ZXI %7, %0, 0
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STR_ZXI %8, %1, 0
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RET_ReallyLR
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...
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