derek.holloway
7502bf64a4
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807 lines
23 KiB
LLVM
807 lines
23 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
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; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
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; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; RUN: llc < %s -mtriple aarch64 -global-isel -global-isel-abort=2 -mattr=+fullfp16 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI-FP16
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; CHECK-GI-FP16: warning: Instruction selection used fallback path for testmswbf
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; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for testmsxbf
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; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for testpswbf
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; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for testpsxbf
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; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for testzswbf
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; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for testzsxbf
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; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for testaswbf
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; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for testasxbf
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; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for testnswbf
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; CHECK-GI-FP16-NEXT: warning: Instruction selection used fallback path for testnsxbf
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; Round towards minus infinity (fcvtms).
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define i32 @testmswbf(bfloat %a) {
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; CHECK-LABEL: testmswbf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
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; CHECK-NEXT: mov w8, #32767 // =0x7fff
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: frintm s0, s0
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w10, w9, #16, #1
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; CHECK-NEXT: add w8, w9, w8
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; CHECK-NEXT: add w8, w10, w8
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: fcvtzs w0, s0
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; CHECK-NEXT: ret
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entry:
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%r = call bfloat @llvm.floor.bf16(bfloat %a)
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%i = call i32 @llvm.fptosi.sat.i32.bf16(bfloat %r)
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ret i32 %i
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}
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define i64 @testmsxbf(bfloat %a) {
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; CHECK-LABEL: testmsxbf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
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; CHECK-NEXT: mov w8, #32767 // =0x7fff
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: frintm s0, s0
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w10, w9, #16, #1
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; CHECK-NEXT: add w8, w9, w8
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; CHECK-NEXT: add w8, w10, w8
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: fcvtzs x0, s0
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; CHECK-NEXT: ret
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entry:
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%r = call bfloat @llvm.floor.bf16(bfloat %a)
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%i = call i64 @llvm.fptosi.sat.i64.bf16(bfloat %r)
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ret i64 %i
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}
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define i32 @testmswh(half %a) {
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; CHECK-CVT-LABEL: testmswh:
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; CHECK-CVT: // %bb.0: // %entry
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; CHECK-CVT-NEXT: fcvt s0, h0
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; CHECK-CVT-NEXT: frintm s0, s0
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; CHECK-CVT-NEXT: fcvt h0, s0
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; CHECK-CVT-NEXT: fcvt s0, h0
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; CHECK-CVT-NEXT: fcvtzs w0, s0
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; CHECK-CVT-NEXT: ret
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;
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; CHECK-FP16-LABEL: testmswh:
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; CHECK-FP16: // %bb.0: // %entry
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; CHECK-FP16-NEXT: fcvtms w0, h0
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; CHECK-FP16-NEXT: ret
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;
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; CHECK-GI-LABEL: testmswh:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fcvt s0, h0
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; CHECK-GI-NEXT: frintm s0, s0
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; CHECK-GI-NEXT: fcvt h0, s0
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; CHECK-GI-NEXT: fcvt s0, h0
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; CHECK-GI-NEXT: fcvtzs w0, s0
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; CHECK-GI-NEXT: ret
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;
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; CHECK-GI-FP16-LABEL: testmswh:
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; CHECK-GI-FP16: // %bb.0: // %entry
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; CHECK-GI-FP16-NEXT: fcvtms w0, h0
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; CHECK-GI-FP16-NEXT: ret
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entry:
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%r = call half @llvm.floor.f16(half %a)
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%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
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ret i32 %i
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}
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define i64 @testmsxh(half %a) {
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; CHECK-CVT-LABEL: testmsxh:
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; CHECK-CVT: // %bb.0: // %entry
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; CHECK-CVT-NEXT: fcvt s0, h0
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; CHECK-CVT-NEXT: frintm s0, s0
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; CHECK-CVT-NEXT: fcvt h0, s0
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; CHECK-CVT-NEXT: fcvt s0, h0
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; CHECK-CVT-NEXT: fcvtzs x0, s0
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; CHECK-CVT-NEXT: ret
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;
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; CHECK-FP16-LABEL: testmsxh:
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; CHECK-FP16: // %bb.0: // %entry
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; CHECK-FP16-NEXT: fcvtms x0, h0
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; CHECK-FP16-NEXT: ret
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;
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; CHECK-GI-LABEL: testmsxh:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fcvt s0, h0
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; CHECK-GI-NEXT: frintm s0, s0
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; CHECK-GI-NEXT: fcvt h0, s0
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; CHECK-GI-NEXT: fcvt s0, h0
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; CHECK-GI-NEXT: fcvtzs x0, s0
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; CHECK-GI-NEXT: ret
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;
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; CHECK-GI-FP16-LABEL: testmsxh:
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; CHECK-GI-FP16: // %bb.0: // %entry
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; CHECK-GI-FP16-NEXT: fcvtms x0, h0
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; CHECK-GI-FP16-NEXT: ret
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entry:
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%r = call half @llvm.floor.f16(half %a)
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%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
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ret i64 %i
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}
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define i32 @testmsws(float %a) {
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; CHECK-LABEL: testmsws:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtms w0, s0
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; CHECK-NEXT: ret
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entry:
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%r = call float @llvm.floor.f32(float %a)
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%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
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ret i32 %i
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}
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define i64 @testmsxs(float %a) {
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; CHECK-LABEL: testmsxs:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtms x0, s0
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; CHECK-NEXT: ret
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entry:
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%r = call float @llvm.floor.f32(float %a)
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%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
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ret i64 %i
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}
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define i32 @testmswd(double %a) {
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; CHECK-LABEL: testmswd:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtms w0, d0
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; CHECK-NEXT: ret
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entry:
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%r = call double @llvm.floor.f64(double %a)
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%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
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ret i32 %i
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}
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define i64 @testmsxd(double %a) {
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; CHECK-LABEL: testmsxd:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtms x0, d0
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; CHECK-NEXT: ret
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entry:
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%r = call double @llvm.floor.f64(double %a)
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%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
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ret i64 %i
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}
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; Round towards plus infinity (fcvtps).
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define i32 @testpswbf(bfloat %a) {
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; CHECK-LABEL: testpswbf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
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; CHECK-NEXT: mov w8, #32767 // =0x7fff
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: frintp s0, s0
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w10, w9, #16, #1
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; CHECK-NEXT: add w8, w9, w8
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; CHECK-NEXT: add w8, w10, w8
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: fcvtzs w0, s0
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; CHECK-NEXT: ret
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entry:
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%r = call bfloat @llvm.ceil.bf16(bfloat %a)
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%i = call i32 @llvm.fptosi.sat.i32.bf16(bfloat %r)
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ret i32 %i
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}
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define i64 @testpsxbf(bfloat %a) {
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; CHECK-LABEL: testpsxbf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
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; CHECK-NEXT: mov w8, #32767 // =0x7fff
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: frintp s0, s0
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w10, w9, #16, #1
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; CHECK-NEXT: add w8, w9, w8
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; CHECK-NEXT: add w8, w10, w8
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: fcvtzs x0, s0
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; CHECK-NEXT: ret
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entry:
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%r = call bfloat @llvm.ceil.bf16(bfloat %a)
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%i = call i64 @llvm.fptosi.sat.i64.bf16(bfloat %r)
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ret i64 %i
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}
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define i32 @testpswh(half %a) {
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; CHECK-CVT-LABEL: testpswh:
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; CHECK-CVT: // %bb.0: // %entry
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; CHECK-CVT-NEXT: fcvt s0, h0
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; CHECK-CVT-NEXT: frintp s0, s0
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; CHECK-CVT-NEXT: fcvt h0, s0
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; CHECK-CVT-NEXT: fcvt s0, h0
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; CHECK-CVT-NEXT: fcvtzs w0, s0
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; CHECK-CVT-NEXT: ret
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;
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; CHECK-FP16-LABEL: testpswh:
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; CHECK-FP16: // %bb.0: // %entry
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; CHECK-FP16-NEXT: fcvtps w0, h0
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; CHECK-FP16-NEXT: ret
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;
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; CHECK-GI-LABEL: testpswh:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fcvt s0, h0
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; CHECK-GI-NEXT: frintp s0, s0
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; CHECK-GI-NEXT: fcvt h0, s0
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; CHECK-GI-NEXT: fcvt s0, h0
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; CHECK-GI-NEXT: fcvtzs w0, s0
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; CHECK-GI-NEXT: ret
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;
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; CHECK-GI-FP16-LABEL: testpswh:
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; CHECK-GI-FP16: // %bb.0: // %entry
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; CHECK-GI-FP16-NEXT: fcvtps w0, h0
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; CHECK-GI-FP16-NEXT: ret
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entry:
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%r = call half @llvm.ceil.f16(half %a)
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%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
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ret i32 %i
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}
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define i64 @testpsxh(half %a) {
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; CHECK-CVT-LABEL: testpsxh:
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; CHECK-CVT: // %bb.0: // %entry
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; CHECK-CVT-NEXT: fcvt s0, h0
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; CHECK-CVT-NEXT: frintp s0, s0
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; CHECK-CVT-NEXT: fcvt h0, s0
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; CHECK-CVT-NEXT: fcvt s0, h0
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; CHECK-CVT-NEXT: fcvtzs x0, s0
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; CHECK-CVT-NEXT: ret
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;
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; CHECK-FP16-LABEL: testpsxh:
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; CHECK-FP16: // %bb.0: // %entry
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; CHECK-FP16-NEXT: fcvtps x0, h0
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; CHECK-FP16-NEXT: ret
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;
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; CHECK-GI-LABEL: testpsxh:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: fcvt s0, h0
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; CHECK-GI-NEXT: frintp s0, s0
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; CHECK-GI-NEXT: fcvt h0, s0
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; CHECK-GI-NEXT: fcvt s0, h0
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; CHECK-GI-NEXT: fcvtzs x0, s0
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; CHECK-GI-NEXT: ret
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;
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; CHECK-GI-FP16-LABEL: testpsxh:
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; CHECK-GI-FP16: // %bb.0: // %entry
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; CHECK-GI-FP16-NEXT: fcvtps x0, h0
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; CHECK-GI-FP16-NEXT: ret
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entry:
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%r = call half @llvm.ceil.f16(half %a)
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%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
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ret i64 %i
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}
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define i32 @testpsws(float %a) {
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; CHECK-LABEL: testpsws:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtps w0, s0
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; CHECK-NEXT: ret
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entry:
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%r = call float @llvm.ceil.f32(float %a)
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%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
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ret i32 %i
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}
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define i64 @testpsxs(float %a) {
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; CHECK-LABEL: testpsxs:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtps x0, s0
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; CHECK-NEXT: ret
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entry:
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%r = call float @llvm.ceil.f32(float %a)
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%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
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ret i64 %i
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}
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define i32 @testpswd(double %a) {
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; CHECK-LABEL: testpswd:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtps w0, d0
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; CHECK-NEXT: ret
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entry:
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%r = call double @llvm.ceil.f64(double %a)
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%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
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ret i32 %i
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}
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define i64 @testpsxd(double %a) {
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; CHECK-LABEL: testpsxd:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvtps x0, d0
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; CHECK-NEXT: ret
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entry:
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%r = call double @llvm.ceil.f64(double %a)
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%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
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ret i64 %i
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}
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; Round towards zero (fcvtzs).
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define i32 @testzswbf(bfloat %a) {
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; CHECK-LABEL: testzswbf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
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; CHECK-NEXT: mov w8, #32767 // =0x7fff
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: frintz s0, s0
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w10, w9, #16, #1
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; CHECK-NEXT: add w8, w9, w8
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; CHECK-NEXT: add w8, w10, w8
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: fcvtzs w0, s0
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; CHECK-NEXT: ret
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entry:
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%r = call bfloat @llvm.trunc.bf16(bfloat %a)
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%i = call i32 @llvm.fptosi.sat.i32.bf16(bfloat %r)
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ret i32 %i
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}
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define i64 @testzsxbf(bfloat %a) {
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; CHECK-LABEL: testzsxbf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
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; CHECK-NEXT: mov w8, #32767 // =0x7fff
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: frintz s0, s0
|
|
; CHECK-NEXT: fmov w9, s0
|
|
; CHECK-NEXT: ubfx w10, w9, #16, #1
|
|
; CHECK-NEXT: add w8, w9, w8
|
|
; CHECK-NEXT: add w8, w10, w8
|
|
; CHECK-NEXT: lsr w8, w8, #16
|
|
; CHECK-NEXT: fmov s0, w8
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: fcvtzs x0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call bfloat @llvm.trunc.bf16(bfloat %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.bf16(bfloat %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
define i32 @testzswh(half %a) {
|
|
; CHECK-CVT-LABEL: testzswh:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: frintz s0, s0
|
|
; CHECK-CVT-NEXT: fcvt h0, s0
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: fcvtzs w0, s0
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-LABEL: testzswh:
|
|
; CHECK-FP16: // %bb.0: // %entry
|
|
; CHECK-FP16-NEXT: fcvtzs w0, h0
|
|
; CHECK-FP16-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: testzswh:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: frintz s0, s0
|
|
; CHECK-GI-NEXT: fcvt h0, s0
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: fcvtzs w0, s0
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-GI-FP16-LABEL: testzswh:
|
|
; CHECK-GI-FP16: // %bb.0: // %entry
|
|
; CHECK-GI-FP16-NEXT: fcvtzs w0, h0
|
|
; CHECK-GI-FP16-NEXT: ret
|
|
entry:
|
|
%r = call half @llvm.trunc.f16(half %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testzsxh(half %a) {
|
|
; CHECK-CVT-LABEL: testzsxh:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: frintz s0, s0
|
|
; CHECK-CVT-NEXT: fcvt h0, s0
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: fcvtzs x0, s0
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-LABEL: testzsxh:
|
|
; CHECK-FP16: // %bb.0: // %entry
|
|
; CHECK-FP16-NEXT: fcvtzs x0, h0
|
|
; CHECK-FP16-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: testzsxh:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: frintz s0, s0
|
|
; CHECK-GI-NEXT: fcvt h0, s0
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: fcvtzs x0, s0
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-GI-FP16-LABEL: testzsxh:
|
|
; CHECK-GI-FP16: // %bb.0: // %entry
|
|
; CHECK-GI-FP16-NEXT: fcvtzs x0, h0
|
|
; CHECK-GI-FP16-NEXT: ret
|
|
entry:
|
|
%r = call half @llvm.trunc.f16(half %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
define i32 @testzsws(float %a) {
|
|
; CHECK-LABEL: testzsws:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs w0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call float @llvm.trunc.f32(float %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testzsxs(float %a) {
|
|
; CHECK-LABEL: testzsxs:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs x0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call float @llvm.trunc.f32(float %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
define i32 @testzswd(double %a) {
|
|
; CHECK-LABEL: testzswd:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs w0, d0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call double @llvm.trunc.f64(double %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testzsxd(double %a) {
|
|
; CHECK-LABEL: testzsxd:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtzs x0, d0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call double @llvm.trunc.f64(double %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
; Round to nearest, ties away from zero (fcvtas).
|
|
|
|
define i32 @testaswbf(bfloat %a) {
|
|
; CHECK-LABEL: testaswbf:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
|
|
; CHECK-NEXT: mov w8, #32767 // =0x7fff
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: frinta s0, s0
|
|
; CHECK-NEXT: fmov w9, s0
|
|
; CHECK-NEXT: ubfx w10, w9, #16, #1
|
|
; CHECK-NEXT: add w8, w9, w8
|
|
; CHECK-NEXT: add w8, w10, w8
|
|
; CHECK-NEXT: lsr w8, w8, #16
|
|
; CHECK-NEXT: fmov s0, w8
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: fcvtzs w0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call bfloat @llvm.round.bf16(bfloat %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.bf16(bfloat %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testasxbf(bfloat %a) {
|
|
; CHECK-LABEL: testasxbf:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
|
|
; CHECK-NEXT: mov w8, #32767 // =0x7fff
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: frinta s0, s0
|
|
; CHECK-NEXT: fmov w9, s0
|
|
; CHECK-NEXT: ubfx w10, w9, #16, #1
|
|
; CHECK-NEXT: add w8, w9, w8
|
|
; CHECK-NEXT: add w8, w10, w8
|
|
; CHECK-NEXT: lsr w8, w8, #16
|
|
; CHECK-NEXT: fmov s0, w8
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: fcvtzs x0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call bfloat @llvm.round.bf16(bfloat %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.bf16(bfloat %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
define i32 @testaswh(half %a) {
|
|
; CHECK-CVT-LABEL: testaswh:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: frinta s0, s0
|
|
; CHECK-CVT-NEXT: fcvt h0, s0
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: fcvtzs w0, s0
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-LABEL: testaswh:
|
|
; CHECK-FP16: // %bb.0: // %entry
|
|
; CHECK-FP16-NEXT: fcvtas w0, h0
|
|
; CHECK-FP16-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: testaswh:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: frinta s0, s0
|
|
; CHECK-GI-NEXT: fcvt h0, s0
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: fcvtzs w0, s0
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-GI-FP16-LABEL: testaswh:
|
|
; CHECK-GI-FP16: // %bb.0: // %entry
|
|
; CHECK-GI-FP16-NEXT: fcvtas w0, h0
|
|
; CHECK-GI-FP16-NEXT: ret
|
|
entry:
|
|
%r = call half @llvm.round.f16(half %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testasxh(half %a) {
|
|
; CHECK-CVT-LABEL: testasxh:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: frinta s0, s0
|
|
; CHECK-CVT-NEXT: fcvt h0, s0
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: fcvtzs x0, s0
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-LABEL: testasxh:
|
|
; CHECK-FP16: // %bb.0: // %entry
|
|
; CHECK-FP16-NEXT: fcvtas x0, h0
|
|
; CHECK-FP16-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: testasxh:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: frinta s0, s0
|
|
; CHECK-GI-NEXT: fcvt h0, s0
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: fcvtzs x0, s0
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-GI-FP16-LABEL: testasxh:
|
|
; CHECK-GI-FP16: // %bb.0: // %entry
|
|
; CHECK-GI-FP16-NEXT: fcvtas x0, h0
|
|
; CHECK-GI-FP16-NEXT: ret
|
|
entry:
|
|
%r = call half @llvm.round.f16(half %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
define i32 @testasws(float %a) {
|
|
; CHECK-LABEL: testasws:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtas w0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call float @llvm.round.f32(float %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testasxs(float %a) {
|
|
; CHECK-LABEL: testasxs:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtas x0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call float @llvm.round.f32(float %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
define i32 @testaswd(double %a) {
|
|
; CHECK-LABEL: testaswd:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtas w0, d0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call double @llvm.round.f64(double %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testasxd(double %a) {
|
|
; CHECK-LABEL: testasxd:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtas x0, d0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call double @llvm.round.f64(double %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
; Round to nearest, ties to even (fcvtns).
|
|
|
|
define i32 @testnswbf(bfloat %a) {
|
|
; CHECK-LABEL: testnswbf:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
|
|
; CHECK-NEXT: mov w8, #32767 // =0x7fff
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: frintn s0, s0
|
|
; CHECK-NEXT: fmov w9, s0
|
|
; CHECK-NEXT: ubfx w10, w9, #16, #1
|
|
; CHECK-NEXT: add w8, w9, w8
|
|
; CHECK-NEXT: add w8, w10, w8
|
|
; CHECK-NEXT: lsr w8, w8, #16
|
|
; CHECK-NEXT: fmov s0, w8
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: fcvtzs w0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call bfloat @llvm.roundeven.bf16(bfloat %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.bf16(bfloat %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testnsxbf(bfloat %a) {
|
|
; CHECK-LABEL: testnsxbf:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: // kill: def $h0 killed $h0 def $d0
|
|
; CHECK-NEXT: mov w8, #32767 // =0x7fff
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: frintn s0, s0
|
|
; CHECK-NEXT: fmov w9, s0
|
|
; CHECK-NEXT: ubfx w10, w9, #16, #1
|
|
; CHECK-NEXT: add w8, w9, w8
|
|
; CHECK-NEXT: add w8, w10, w8
|
|
; CHECK-NEXT: lsr w8, w8, #16
|
|
; CHECK-NEXT: fmov s0, w8
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: fcvtzs x0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call bfloat @llvm.roundeven.bf16(bfloat %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.bf16(bfloat %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
define i32 @testnswh(half %a) {
|
|
; CHECK-CVT-LABEL: testnswh:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: frintn s0, s0
|
|
; CHECK-CVT-NEXT: fcvt h0, s0
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: fcvtzs w0, s0
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-LABEL: testnswh:
|
|
; CHECK-FP16: // %bb.0: // %entry
|
|
; CHECK-FP16-NEXT: fcvtns w0, h0
|
|
; CHECK-FP16-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: testnswh:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: frintn s0, s0
|
|
; CHECK-GI-NEXT: fcvt h0, s0
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: fcvtzs w0, s0
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-GI-FP16-LABEL: testnswh:
|
|
; CHECK-GI-FP16: // %bb.0: // %entry
|
|
; CHECK-GI-FP16-NEXT: fcvtns w0, h0
|
|
; CHECK-GI-FP16-NEXT: ret
|
|
entry:
|
|
%r = call half @llvm.roundeven.f16(half %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testnsxh(half %a) {
|
|
; CHECK-CVT-LABEL: testnsxh:
|
|
; CHECK-CVT: // %bb.0: // %entry
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: frintn s0, s0
|
|
; CHECK-CVT-NEXT: fcvt h0, s0
|
|
; CHECK-CVT-NEXT: fcvt s0, h0
|
|
; CHECK-CVT-NEXT: fcvtzs x0, s0
|
|
; CHECK-CVT-NEXT: ret
|
|
;
|
|
; CHECK-FP16-LABEL: testnsxh:
|
|
; CHECK-FP16: // %bb.0: // %entry
|
|
; CHECK-FP16-NEXT: fcvtns x0, h0
|
|
; CHECK-FP16-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: testnsxh:
|
|
; CHECK-GI: // %bb.0: // %entry
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: frintn s0, s0
|
|
; CHECK-GI-NEXT: fcvt h0, s0
|
|
; CHECK-GI-NEXT: fcvt s0, h0
|
|
; CHECK-GI-NEXT: fcvtzs x0, s0
|
|
; CHECK-GI-NEXT: ret
|
|
;
|
|
; CHECK-GI-FP16-LABEL: testnsxh:
|
|
; CHECK-GI-FP16: // %bb.0: // %entry
|
|
; CHECK-GI-FP16-NEXT: fcvtns x0, h0
|
|
; CHECK-GI-FP16-NEXT: ret
|
|
entry:
|
|
%r = call half @llvm.roundeven.f16(half %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
define i32 @testnsws(float %a) {
|
|
; CHECK-LABEL: testnsws:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtns w0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call float @llvm.roundeven.f32(float %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testnsxs(float %a) {
|
|
; CHECK-LABEL: testnsxs:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtns x0, s0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call float @llvm.roundeven.f32(float %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
|
|
ret i64 %i
|
|
}
|
|
|
|
define i32 @testnswd(double %a) {
|
|
; CHECK-LABEL: testnswd:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtns w0, d0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call double @llvm.roundeven.f64(double %a)
|
|
%i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
|
|
ret i32 %i
|
|
}
|
|
|
|
define i64 @testnsxd(double %a) {
|
|
; CHECK-LABEL: testnsxd:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: fcvtns x0, d0
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%r = call double @llvm.roundeven.f64(double %a)
|
|
%i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
|
|
ret i64 %i
|
|
}
|