derek.holloway
7502bf64a4
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433 lines
16 KiB
LLVM
433 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64 -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define <4 x i32> @direct_setcc_lt0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: direct_setcc_lt0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: direct_setcc_lt0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%lt0 = icmp slt <4 x i32> %sext, zeroinitializer
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%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <4 x i32> @shuffle_setcc_lt0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: shuffle_setcc_lt0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: dup v0.4s, v0.s[2]
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: shuffle_setcc_lt0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: dup v0.4s, v0.s[2]
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%dup = shufflevector <4 x i32> %sext, <4 x i32> poison, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
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%lt0 = icmp slt <4 x i32> %dup, zeroinitializer
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%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <4 x i32> @direct_setcc_0gt(<4 x i32> %a, <4 x i32> %b, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: direct_setcc_0gt:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: direct_setcc_0gt:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%gt0 = icmp sgt <4 x i32> zeroinitializer, %sext
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%sel = select <4 x i1> %gt0, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <8 x i16> @direct_setcc_lt0_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %x, <8 x i16> %y) {
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; CHECK-SD-LABEL: direct_setcc_lt0_v8i16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.8h, v1.8h, v0.8h
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: direct_setcc_lt0_v8i16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
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; CHECK-GI-NEXT: cmlt v0.8h, v0.8h, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <8 x i16> %a, %b
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%sext = sext <8 x i1> %cmp to <8 x i16>
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%lt0 = icmp slt <8 x i16> %sext, zeroinitializer
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%sel = select <8 x i1> %lt0, <8 x i16> %x, <8 x i16> %y
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ret <8 x i16> %sel
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}
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define <4 x i32> @non_splat_shuffle(<4 x i32> %a, <4 x i32> %b, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: non_splat_shuffle:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
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; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: non_splat_shuffle:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: rev64 v0.4s, v0.4s
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; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%shuf = shufflevector <4 x i32> %sext, <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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%lt0 = icmp slt <4 x i32> %shuf, zeroinitializer
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%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <16 x i8> @bitcast_narrow(<4 x i32> %a, <4 x i32> %b, <16 x i8> %x, <16 x i8> %y) {
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; CHECK-SD-LABEL: bitcast_narrow:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: bitcast_narrow:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%bc = bitcast <4 x i32> %sext to <16 x i8>
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%lt0 = icmp slt <16 x i8> %bc, zeroinitializer
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%sel = select <16 x i1> %lt0, <16 x i8> %x, <16 x i8> %y
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ret <16 x i8> %sel
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}
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define <8 x i16> @chain_shuffle_bitcast(<4 x i32> %a, <4 x i32> %b, <8 x i16> %x, <8 x i16> %y) {
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; CHECK-SD-LABEL: chain_shuffle_bitcast:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: dup v0.4s, v0.s[2]
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: chain_shuffle_bitcast:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: dup v0.4s, v0.s[2]
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; CHECK-GI-NEXT: cmlt v0.8h, v0.8h, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%shuf = shufflevector <4 x i32> %sext, <4 x i32> poison, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
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%bc = bitcast <4 x i32> %shuf to <8 x i16>
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%lt0 = icmp slt <8 x i16> %bc, zeroinitializer
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%sel = select <8 x i1> %lt0, <8 x i16> %x, <8 x i16> %y
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ret <8 x i16> %sel
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}
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define <4 x i32> @setcc_ne0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: setcc_ne0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: setcc_ne0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: cmtst v0.4s, v0.4s, v0.4s
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%ne0 = icmp ne <4 x i32> %sext, zeroinitializer
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%sel = select <4 x i1> %ne0, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <4 x i32> @setcc_ugt0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: setcc_ugt0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: setcc_ugt0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: movi v4.2d, #0000000000000000
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: cmhi v0.4s, v0.4s, v4.4s
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%sext = sext <4 x i1> %cmp to <4 x i32>
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%ugt0 = icmp ugt <4 x i32> %sext, zeroinitializer
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%sel = select <4 x i1> %ugt0, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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; NEGATIVE TEST: Widening bitcast should NOT be optimized
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define <4 x i32> @bitcast_widen_negative(<16 x i8> %a, <16 x i8> %b, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: bitcast_widen_negative:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-NEXT: ret
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%cmp = icmp slt <16 x i8> %a, %b
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%sext = sext <16 x i1> %cmp to <16 x i8>
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%bc = bitcast <16 x i8> %sext to <4 x i32>
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%lt0 = icmp slt <4 x i32> %bc, zeroinitializer
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%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <4 x i32> @smax_setcc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: smax_setcc:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v2.4s, v3.4s, v2.4s
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v5.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: smax_setcc:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v2.4s
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; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b
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; CHECK-GI-NEXT: ret
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%cmp1 = icmp slt <4 x i32> %a, %b
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%sext1 = sext <4 x i1> %cmp1 to <4 x i32>
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%cmp2 = icmp slt <4 x i32> %c, %d
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%sext2 = sext <4 x i1> %cmp2 to <4 x i32>
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%smax = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %sext1, <4 x i32> %sext2)
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%lt0 = icmp slt <4 x i32> %smax, zeroinitializer
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%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <4 x i32> @smin_setcc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: smin_setcc:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v2.4s, v3.4s, v2.4s
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
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; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v5.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: smin_setcc:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v2.4s
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; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b
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; CHECK-GI-NEXT: ret
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%cmp1 = icmp slt <4 x i32> %a, %b
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%sext1 = sext <4 x i1> %cmp1 to <4 x i32>
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%cmp2 = icmp slt <4 x i32> %c, %d
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%sext2 = sext <4 x i1> %cmp2 to <4 x i32>
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%smin = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %sext1, <4 x i32> %sext2)
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%lt0 = icmp slt <4 x i32> %smin, zeroinitializer
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%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <4 x i32> @umax_setcc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: umax_setcc:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v2.4s, v3.4s, v2.4s
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
|
|
; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: umax_setcc:
|
|
; CHECK-GI: // %bb.0:
|
|
; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v2.4s
|
|
; CHECK-GI-NEXT: umax v0.4s, v0.4s, v1.4s
|
|
; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
|
|
; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-GI-NEXT: ret
|
|
%cmp1 = icmp slt <4 x i32> %a, %b
|
|
%sext1 = sext <4 x i1> %cmp1 to <4 x i32>
|
|
%cmp2 = icmp slt <4 x i32> %c, %d
|
|
%sext2 = sext <4 x i1> %cmp2 to <4 x i32>
|
|
%umax = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %sext1, <4 x i32> %sext2)
|
|
%lt0 = icmp slt <4 x i32> %umax, zeroinitializer
|
|
%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
|
|
ret <4 x i32> %sel
|
|
}
|
|
|
|
define <4 x i32> @umin_setcc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %x, <4 x i32> %y) {
|
|
; CHECK-SD-LABEL: umin_setcc:
|
|
; CHECK-SD: // %bb.0:
|
|
; CHECK-SD-NEXT: cmgt v2.4s, v3.4s, v2.4s
|
|
; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
|
|
; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: umin_setcc:
|
|
; CHECK-GI: // %bb.0:
|
|
; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v2.4s
|
|
; CHECK-GI-NEXT: umin v0.4s, v0.4s, v1.4s
|
|
; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
|
|
; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-GI-NEXT: ret
|
|
%cmp1 = icmp slt <4 x i32> %a, %b
|
|
%sext1 = sext <4 x i1> %cmp1 to <4 x i32>
|
|
%cmp2 = icmp slt <4 x i32> %c, %d
|
|
%sext2 = sext <4 x i1> %cmp2 to <4 x i32>
|
|
%umin = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %sext1, <4 x i32> %sext2)
|
|
%lt0 = icmp slt <4 x i32> %umin, zeroinitializer
|
|
%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
|
|
ret <4 x i32> %sel
|
|
}
|
|
|
|
define <4 x i32> @select_setcc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %x, <4 x i32> %y) {
|
|
; CHECK-SD-LABEL: select_setcc:
|
|
; CHECK-SD: // %bb.0:
|
|
; CHECK-SD-NEXT: cmgt v2.4s, v3.4s, v2.4s
|
|
; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-SD-NEXT: cmgt v1.4s, v5.4s, v4.4s
|
|
; CHECK-SD-NEXT: bif v0.16b, v2.16b, v1.16b
|
|
; CHECK-SD-NEXT: bsl v0.16b, v6.16b, v7.16b
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: select_setcc:
|
|
; CHECK-GI: // %bb.0:
|
|
; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v2.4s
|
|
; CHECK-GI-NEXT: cmgt v2.4s, v5.4s, v4.4s
|
|
; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
|
|
; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
|
|
; CHECK-GI-NEXT: bsl v0.16b, v6.16b, v7.16b
|
|
; CHECK-GI-NEXT: ret
|
|
%cmp1 = icmp slt <4 x i32> %a, %b
|
|
%sext1 = sext <4 x i1> %cmp1 to <4 x i32>
|
|
%cmp2 = icmp slt <4 x i32> %c, %d
|
|
%sext2 = sext <4 x i1> %cmp2 to <4 x i32>
|
|
%cond = icmp slt <4 x i32> %e, %f
|
|
%sel1 = select <4 x i1> %cond, <4 x i32> %sext1, <4 x i32> %sext2
|
|
%lt0 = icmp slt <4 x i32> %sel1, zeroinitializer
|
|
%sel2 = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
|
|
ret <4 x i32> %sel2
|
|
}
|
|
|
|
define <4 x i32> @and_setcc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %x, <4 x i32> %y) {
|
|
; CHECK-SD-LABEL: and_setcc:
|
|
; CHECK-SD: // %bb.0:
|
|
; CHECK-SD-NEXT: cmgt v2.4s, v3.4s, v2.4s
|
|
; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b
|
|
; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: and_setcc:
|
|
; CHECK-GI: // %bb.0:
|
|
; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v2.4s
|
|
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
|
|
; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
|
|
; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-GI-NEXT: ret
|
|
%cmp1 = icmp slt <4 x i32> %a, %b
|
|
%sext1 = sext <4 x i1> %cmp1 to <4 x i32>
|
|
%cmp2 = icmp slt <4 x i32> %c, %d
|
|
%sext2 = sext <4 x i1> %cmp2 to <4 x i32>
|
|
%and = and <4 x i32> %sext1, %sext2
|
|
%lt0 = icmp slt <4 x i32> %and, zeroinitializer
|
|
%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
|
|
ret <4 x i32> %sel
|
|
}
|
|
|
|
define <4 x i32> @or_setcc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %x, <4 x i32> %y) {
|
|
; CHECK-SD-LABEL: or_setcc:
|
|
; CHECK-SD: // %bb.0:
|
|
; CHECK-SD-NEXT: cmgt v2.4s, v3.4s, v2.4s
|
|
; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b
|
|
; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: or_setcc:
|
|
; CHECK-GI: // %bb.0:
|
|
; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v2.4s
|
|
; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b
|
|
; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
|
|
; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-GI-NEXT: ret
|
|
%cmp1 = icmp slt <4 x i32> %a, %b
|
|
%sext1 = sext <4 x i1> %cmp1 to <4 x i32>
|
|
%cmp2 = icmp slt <4 x i32> %c, %d
|
|
%sext2 = sext <4 x i1> %cmp2 to <4 x i32>
|
|
%or = or <4 x i32> %sext1, %sext2
|
|
%lt0 = icmp slt <4 x i32> %or, zeroinitializer
|
|
%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
|
|
ret <4 x i32> %sel
|
|
}
|
|
|
|
define <4 x i32> @xor_setcc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %x, <4 x i32> %y) {
|
|
; CHECK-SD-LABEL: xor_setcc:
|
|
; CHECK-SD: // %bb.0:
|
|
; CHECK-SD-NEXT: cmgt v2.4s, v3.4s, v2.4s
|
|
; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-SD-NEXT: eor v0.16b, v0.16b, v2.16b
|
|
; CHECK-SD-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: xor_setcc:
|
|
; CHECK-GI: // %bb.0:
|
|
; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
|
|
; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v2.4s
|
|
; CHECK-GI-NEXT: eor v0.16b, v0.16b, v1.16b
|
|
; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
|
|
; CHECK-GI-NEXT: bsl v0.16b, v4.16b, v5.16b
|
|
; CHECK-GI-NEXT: ret
|
|
%cmp1 = icmp slt <4 x i32> %a, %b
|
|
%sext1 = sext <4 x i1> %cmp1 to <4 x i32>
|
|
%cmp2 = icmp slt <4 x i32> %c, %d
|
|
%sext2 = sext <4 x i1> %cmp2 to <4 x i32>
|
|
%xor = xor <4 x i32> %sext1, %sext2
|
|
%lt0 = icmp slt <4 x i32> %xor, zeroinitializer
|
|
%sel = select <4 x i1> %lt0, <4 x i32> %x, <4 x i32> %y
|
|
ret <4 x i32> %sel
|
|
}
|