derek.holloway
7502bf64a4
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158 lines
6.2 KiB
LLVM
158 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sme -relocation-model=pic < %s | FileCheck %s
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@x = external thread_local local_unnamed_addr global i32, align 4
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define i32 @load_tls_streaming_compat() nounwind "aarch64_pstate_sm_compatible" {
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; CHECK-LABEL: load_tls_streaming_compat:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill
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; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
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; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
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; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
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; CHECK-NEXT: mrs x8, SVCR
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; CHECK-NEXT: tbz w8, #0, .LBB0_2
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: smstop sm
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; CHECK-NEXT: .LBB0_2: // %entry
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; CHECK-NEXT: adrp x0, :tlsdesc:x
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; CHECK-NEXT: ldr x1, [x0, :tlsdesc_lo12:x]
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; CHECK-NEXT: add x0, x0, :tlsdesc_lo12:x
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; CHECK-NEXT: .tlsdesccall x
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; CHECK-NEXT: blr x1
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; CHECK-NEXT: tbz w8, #0, .LBB0_4
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; CHECK-NEXT: // %bb.3: // %entry
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; CHECK-NEXT: smstart sm
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; CHECK-NEXT: .LBB0_4: // %entry
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; CHECK-NEXT: mrs x8, TPIDR_EL0
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; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
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; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
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; CHECK-NEXT: ldr w0, [x8, x0]
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; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
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; CHECK-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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entry:
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%0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x)
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%1 = load i32, ptr %0, align 4
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ret i32 %1
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}
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define i32 @load_tls_streaming() nounwind "aarch64_pstate_sm_enabled" {
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; CHECK-LABEL: load_tls_streaming:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill
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; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
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; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
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; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill
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; CHECK-NEXT: smstop sm
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; CHECK-NEXT: adrp x0, :tlsdesc:x
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; CHECK-NEXT: ldr x1, [x0, :tlsdesc_lo12:x]
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; CHECK-NEXT: add x0, x0, :tlsdesc_lo12:x
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; CHECK-NEXT: .tlsdesccall x
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; CHECK-NEXT: blr x1
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; CHECK-NEXT: smstart sm
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; CHECK-NEXT: mrs x8, TPIDR_EL0
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; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
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; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
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; CHECK-NEXT: ldr w0, [x8, x0]
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; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload
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; CHECK-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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entry:
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%0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x)
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%1 = load i32, ptr %0, align 4
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ret i32 %1
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}
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define i32 @load_tls_shared_za() nounwind "aarch64_inout_za" {
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; CHECK-LABEL: load_tls_shared_za:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
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; CHECK-NEXT: mov x29, sp
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: rdsvl x8, #1
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: msub x9, x8, x8, x9
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; CHECK-NEXT: mov sp, x9
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; CHECK-NEXT: sub x10, x29, #16
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; CHECK-NEXT: stp x9, x8, [x29, #-16]
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; CHECK-NEXT: msr TPIDR2_EL0, x10
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; CHECK-NEXT: adrp x0, :tlsdesc:x
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; CHECK-NEXT: ldr x1, [x0, :tlsdesc_lo12:x]
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; CHECK-NEXT: add x0, x0, :tlsdesc_lo12:x
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; CHECK-NEXT: .tlsdesccall x
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; CHECK-NEXT: blr x1
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; CHECK-NEXT: mrs x8, TPIDR_EL0
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; CHECK-NEXT: ldr w8, [x8, x0]
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; CHECK-NEXT: smstart za
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; CHECK-NEXT: mrs x9, TPIDR2_EL0
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; CHECK-NEXT: sub x0, x29, #16
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; CHECK-NEXT: cbnz x9, .LBB2_2
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: bl __arm_tpidr2_restore
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; CHECK-NEXT: .LBB2_2: // %entry
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; CHECK-NEXT: mov w0, w8
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; CHECK-NEXT: msr TPIDR2_EL0, xzr
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; CHECK-NEXT: mov sp, x29
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; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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entry:
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%0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x)
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%1 = load i32, ptr %0, align 4
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ret i32 %1
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}
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define i32 @load_tls_streaming_shared_za() nounwind "aarch64_inout_za" "aarch64_pstate_sm_enabled" {
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; CHECK-LABEL: load_tls_streaming_shared_za:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: stp d15, d14, [sp, #-96]! // 16-byte Folded Spill
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; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
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; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
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; CHECK-NEXT: stp x29, x30, [sp, #64] // 16-byte Folded Spill
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; CHECK-NEXT: add x29, sp, #64
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; CHECK-NEXT: str x19, [sp, #80] // 8-byte Spill
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: rdsvl x8, #1
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; CHECK-NEXT: mov x9, sp
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; CHECK-NEXT: msub x9, x8, x8, x9
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; CHECK-NEXT: mov sp, x9
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; CHECK-NEXT: stp x9, x8, [x29, #-80]
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; CHECK-NEXT: smstop sm
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; CHECK-NEXT: sub x8, x29, #80
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; CHECK-NEXT: msr TPIDR2_EL0, x8
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; CHECK-NEXT: adrp x0, :tlsdesc:x
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; CHECK-NEXT: ldr x1, [x0, :tlsdesc_lo12:x]
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; CHECK-NEXT: add x0, x0, :tlsdesc_lo12:x
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; CHECK-NEXT: .tlsdesccall x
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; CHECK-NEXT: blr x1
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; CHECK-NEXT: smstart sm
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; CHECK-NEXT: mrs x8, TPIDR_EL0
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; CHECK-NEXT: ldr w8, [x8, x0]
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; CHECK-NEXT: smstart za
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; CHECK-NEXT: mrs x9, TPIDR2_EL0
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; CHECK-NEXT: sub x0, x29, #80
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; CHECK-NEXT: cbnz x9, .LBB3_2
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: bl __arm_tpidr2_restore
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; CHECK-NEXT: .LBB3_2: // %entry
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; CHECK-NEXT: mov w0, w8
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; CHECK-NEXT: msr TPIDR2_EL0, xzr
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; CHECK-NEXT: sub sp, x29, #64
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; CHECK-NEXT: ldp x29, x30, [sp, #64] // 16-byte Folded Reload
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; CHECK-NEXT: ldr x19, [sp, #80] // 8-byte Reload
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; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
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; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
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; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
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; CHECK-NEXT: ldp d15, d14, [sp], #96 // 16-byte Folded Reload
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; CHECK-NEXT: ret
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entry:
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%0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x)
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%1 = load i32, ptr %0, align 4
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ret i32 %1
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}
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